Intel IXP43X manual UTPOPDATA4, UTPOPDATA75, UTPOPADDR40, Utpopfci, Utpipclk

Page 38

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

 

 

Type

Pull

 

 

Name

Up/

Description

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data

 

 

 

 

from the processor to an ATM UTOPIA Level 2-compliant PHY.

UTP_OP_DATA[4] /

TRI

No

MII Mode of Operation:

ETHA_TXEN

Indicates that the PHY is being presented with nibbles on the MII interface.

 

 

 

 

 

 

Asserted synchronously, with respect to ETHA_TXCLK, at the first nibble of the

 

 

 

 

preamble, and remains asserted until all the nibbles of a frame are presented.

 

 

 

 

This MAC does not contain hardware hashing capabilities that are local to the

 

 

 

 

interface.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

UTP_OP_DATA[7:5]

TRI

No

UTOPIA Level 2 output data. Also known as UTP_TX_DATA. Used to send data

 

 

 

 

from the processor to an ATM UTOPIA Level 2-compliant PHY.

 

 

 

 

Transmit PHY address bus. Used by the processor when operating in MPHY

 

 

 

 

mode to poll and select a single PHY at any given time.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

UTP_OP_ADDR[4:0]

I/O

Yes

the interface/signal should be pulled high with a 10-KΩresistor. When this

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

 

 

 

 

fuse and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Output data flow control input: Also known as the TXFULL/CLAV

 

 

 

 

signal.

 

 

 

 

Used to inform the processor, the ability of each polled PHY to receive a complete

 

 

 

 

cell. For

 

 

 

 

cell-level flow control in an MPHY environment, TxClav is an active high tri-

 

 

 

 

stateable signal from the MPHY to ATM layer.

 

 

 

 

The UTP_OP_FCI is connected to multiple MPHY devices. It sees the logic high

UTP_OP_FCI

I

Yes

generated by the PHY, one clock after the given PHY address is asserted and a

full cell can be received by the PHY. The UTP_OP_FCI sees a logic low generated

 

 

 

 

by the PHY one clock cycle, after the PHY address is asserted, and a full cell

 

 

 

 

cannot be received by the PHY.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 Receive clock input. Also known as UTP_RX_CLK.

 

 

 

 

This signal is used to synchronize all UTOPIA Level 2-received inputs to the rising

 

 

 

 

edge of the UTP_IP_CLK.

 

 

 

 

MII Mode of Operation:

UTP_IP_CLK /

I

Yes

Externally supplied receive clock.

ETHA_RXCLK

• 25 MHz for 100 Mbps operation

 

 

 

 

 

 

• 2.5 MHz for 10 Mbps

 

 

 

 

This MAC interface does not contain hardware hashing capabilities that are local

 

 

 

 

to the interface.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

††

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

 

interface.

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

38

Document Number: 316844; Revision: 001US

Page 37 Page 39
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Page 37 Page 39
Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name DescriptionList of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol DescriptionDDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately EthernetType Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface ExampleDesign Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPADDR40 UTPOPDATA4UTPOPDATA75 UtpopfciUtpipsoc ClavUtpipfci ETHARXDATA30 EtharxclkUTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40HSS Interface Device ConnectionHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 PciclkinPCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection FieldPCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling§ § General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGACrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDrasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / DdrcasnDDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations SizeaAddress Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsTiming Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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