Intel IXP43X PCI Host/Option Interface Pin Description Sheet 2, PCIGNTN30 outputs of the Host

Page 49

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 18.

PCI Host/Option Interface Pin Description (Sheet 2 of 3)

 

 

 

 

 

 

 

 

Type

 

Option

 

Name

 

Device-Pin Connection

Type

Description

 

Field

 

 

 

Field

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_IRDY_N

 

I/O

the two devices.

I/O

Initiator Ready

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_STOP_N

 

I/O

the two devices.

I/O

Stop

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_PERR_N

 

I/O

the two devices.

I/O

Parity Error

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_SERR_N

 

I/O

the two devices.

I/O

System Error

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect signal to same pin between

 

 

PCI_DEVSEL_N

 

I/O

the two devices.

I/O

Device Select

 

 

 

Connect a 10-KΩpull-up resistor.

 

 

 

 

 

 

 

 

 

 

 

Connect one of the higher order PCI

 

 

PCI_IDSEL

 

I

address signals to the Device.

I

Initialization Device Select

 

Connect a 10K pull-up resistor to the

 

 

 

 

 

 

 

 

Host.

 

 

 

 

 

 

 

 

 

 

 

From the Option device, connect output

 

Arbitration Request

 

 

 

 

On the Option device, these signals are not

 

 

 

signal PCI_REQ_N[0] to one of the

 

 

 

 

PCI_REQ_N[3:0] inputs to the Host.

 

used, they should be pulled high with a 10-KΩ

PCI_REQ_N[3:1]

 

I

Note: the PCI_REQ_N[n] must

I

resistor.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where n must

 

 

 

where n must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

From the Option device, connect output

 

Arbitration Request

 

 

 

 

On the Option device, this signal is an output

 

 

 

PCI_REQ_N[0] to one of the

 

 

 

 

PCI_REQ_N[3:0] inputs to the Host.

 

and must be connected to one of the

PCI_REQ_N[0]

 

I

Note: the PCI_REQ_N[n] must

O

PCI_REQ_N[3:0] inputs to the Host.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where n must

 

 

 

where n must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Connect one of the Host outputs

 

 

 

 

 

PCI_GNT_N[3:0] to PCI_GNT_N[0]

 

Arbitration Grant

 

 

 

input to the Option.

 

 

 

 

 

On the Option device, these signals are not

PCI_GNT_N[3:1]

 

O

Note: the PCI_GNT_N[n] must

O

 

used, they should be pulled high with a 10-KΩ

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

resistor.

 

 

 

where n must be the same number in

 

 

 

 

 

 

 

 

 

the square bracket.

 

 

 

 

 

 

 

 

 

 

 

Connect one of the Host outputs

 

Arbitration Grant

 

 

 

 

On the Option device, this signal is an input

 

 

 

PCI_GNT_N[3:0] to PCI_GNT_N[0]

 

 

 

 

input to the Option.

 

and must be connected to one of the

PCI_GNT_N[0]

 

O

Note: the PCI_GNT_N[n] must

I

PCI_GNT_N[3:0] outputs of the Host.

 

Note: The PCI_REQ_N[n] must correspond

 

 

 

correspond to the PCI_GNT_N[n],

 

 

 

 

 

to the PCI_GNT_N[n], where n must

 

 

 

where n must be the same number in

 

 

 

 

 

be the same number in the square

 

 

 

the square bracket.

 

 

 

 

 

bracket.

 

 

 

 

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

49

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Page 48 Page 50
Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsHDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII MII Interface Example Gpio InterfaceUSB Interface Gpio Signal RecommendationsDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDdrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupGroup Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §
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