Intel IXP43X manual Boot/Reset Strapping Configuration Sheet 2

Page 23

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 6.

Boot/Reset Strapping Configuration (Sheet 2 of 2)

 

 

 

 

 

 

Name

 

Function

 

 

Description

 

 

 

 

 

 

 

 

1

= EX_IOWAIT_N is sampled during the read/write expansion bus cycles for Chip

 

 

 

Select 0.

 

 

 

 

 

0

= EX_IOWAIT_N is ignored for read and write cycles to Chip select 0 if

 

 

 

EXP_TIMING_CS0 is configured to Intel mode that is mentioned in Intel® IXP43X

 

 

 

Product Line of Network Processors Datasheet and Intel® IXP43X Product Line of

 

 

 

Network Processors Developer’s Manual.

 

 

 

Typically, IOWAIT_CS0 must be pulled down to Vss when attaching a Synchronous

EX_ADDR[10]

 

IOWAIT_CS0

Intel StrataFlash® on Chip Select 0 since the default mode for EXP_TIMING_CS0 is

 

Intel mode and EX_IOWAIT_N is an unknown value for Synchronous Intel

 

 

 

StrataFlash.

 

 

 

 

 

If the board does not connect the Synchronous Intel StrataFlash WAIT pin to

 

 

 

EX_WAIT_N (and the board guarantees EX_IOWAIT_N is pulled up), the value of

 

 

 

IOWAIT_CS0 is a don’t-care, since EX_IOWAIT_N will not be asserted.

 

 

 

When EXP_TIMING_CS0 is reconfigured to Intel Synchronous mode during

 

 

 

boot-up (for synchronous Intel chips), the expansion bus controller ignores

 

 

 

EX_IOWAIT_N during read and write cycles since the WAIT functionality is

 

 

 

determined from the EXP_SYNCINTEL_COUNT and EXP_TIMING_CS registers.

 

 

 

 

 

EX_ADDR[9]

 

EXP_MEM_DRIVE

Refer to table found in EX_ADDR[5].

 

 

 

 

 

 

 

 

 

Controls the USB clock select.

 

 

 

 

1

= USB Host/Device clock is generated internally

EX_ADDR[8]

 

USB Clock

0

= USB Device clock is generated from GPIO[0].

 

 

 

When generating a spread spectrum clock on OSC_IN, GPIO[1] can be driven from

 

 

 

the system board to generate a 48 MHz clock for the USB Host.

 

 

 

 

 

 

 

Selects the data bus width of the FLASH memory device found on Chip Select 0.

EX_ADDR[7]

 

32_FLASH

Refer to 8/16_FLASH bit (Bit 0) of this register as well.

 

0

= 8 or 16-bit data bus size (must be pulled down during address strapping)

 

 

 

 

 

 

1

= not supported

 

 

 

 

 

 

 

 

EX_ADDR[6]

 

(Reserved)

(Reserved)

 

 

 

 

 

 

 

 

 

Expansion bus low/medium/high drive strength. The drive strength depends on

 

 

 

EXP_DRIVE and EXP_MEM_DRIVE configuration bits.

 

 

 

EXP_MEM_DRIVE

EXP_DRIVE

Expansion drive strength

EX_ADDR[5]

 

EXP_DRIVE

------------------------------------------------------------------------------------

 

 

0

0

Reserved

 

 

 

 

 

 

 

 

0

1

Medium Drive

 

 

 

 

1

0

Low Drive

 

 

 

 

1

1

High Drive

 

 

 

 

 

 

 

Sets the clock speed of the PCI Interface

EX_ADDR[4]

 

PCI_CLK

0

= 33 MHz (must be pulled down during address strapping)

 

 

 

1

= not supported

 

 

 

 

 

 

EX_ADDR[3]

 

(Reserved)

(Reserved). EX_ADDR[3] must not be pulled down during address strapping. This

 

bit must be written to ‘1’ if performing a write to this register.

 

 

 

 

 

 

 

 

 

 

 

Enables the PCI Controller Arbiter

 

EX_ADDR[2]

 

PCI_ARB

0

= PCI arbiter disabled

 

 

 

 

1

= PCI arbiter enabled

 

 

 

 

 

 

 

 

Configures the PCI Controller as PCI Bus Host

EX_ADDR[1]

 

PCI_HOST

0

= PCI as non-host

 

 

 

 

1

= PCI as host

 

 

 

 

 

 

 

 

 

Specifies the data bus width of the FLASH memory device found on Chip Select 0.

EX_ADDR[0]

 

8/16_FLASH

8/16_FLASH

Data bus size

 

 

 

0

16-bit

 

 

 

 

 

 

 

 

 

 

1

8-bit

 

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

23

Image 23
Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content OverviewTerm Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1List of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram InterfaceName Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 TypeDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio InterfaceDesign Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40ETHARXDATA30 Etharxclk ClavUtpipfci UtpipsocUTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7Device Connection HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 PciintanType Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations§ § Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsCrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHzParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramDcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / DdrrasnDDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram ConfigurationsTechnology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select TotalDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsPrinted Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing RelationshipsTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §