Intel IXP43X manual DDR Sdram

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Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 25. Processor-DDRII/I SDRAM Interface

	DDRII/I_DQ[31:0]	DATA[31:0]	DQ[31:0]
	DDRII/I_MA[13:0]	ADDRESS[13:0]	A[13:0]
Processors	DDRII/I_CK[2:0]	CLOCK[2:0], CLOCK#[2:0]	CK[2:0]
	DDRII/I_CK_N[2:0]	CLOCK[2:0], CLOCK#[2:0]	CK#[2:0]
	DDRII/I_CK_N[2:0]		CK#[2:0]

Product Line of Network	DDRII/I_CKE[1:0]	CLOCK ENABLE[1:0]	CKE[1:0]
	DDRII/I_CS_N[1:0]	CHIP SELECT#[1:0]	CS#[1:0]	DDR SDRAM
	DDRII/I_BA[1:0]	BANK SELECT[1:0]	BA[1:0]
	DDRII/I_CB[7:0]	ECC DATA[7:0]	DQ[7:0]
IXP43X	DDRII/I_DM[4:0]	DATA MASK[4:0]	DM[4:0]
Intel®	DDRII/I_DQS[4:0]	DATA STROBE[4:0]	DQS[4:0]
	DDRII/I_DQS[4:0]	DATA STROBE[4:0]	DQS[4:0]
	DDRII/I_WE_N		WE#
	DDRII/I_RAS_N	WRITE#, RAS#, CAS#	RAS#
	DDRII/I_CAS_N		CAS#
				B3986 -003

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	73

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsHDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII MII Interface Example Gpio InterfaceUSB Interface Gpio Signal RecommendationsDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDdrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupGroup Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §