Intel IXP43X manual Stack-Up Selection, Component Placement on a PCB

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Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 16. Component Placement on a PCB


					C
		Medium Frequency			C
		Medium Frequency			O
					N
					N
		High Frequency			N
		Components			E
		Components			C
					C
					T
					O
Analog Circuit		Low Frequency			R
Analog Circuit		Low Frequency

PCB

B2264-01

•Place noisy parts (clock, processor, video, and so on.) at least 1.5 – 3 inches away from the edge of the printed circuit board

•Do not place noisy components close to internal/external cables

—Any loose cables picks up noise and acts as an antenna to radiate that noise

—Be aware of the peak in-rush surge current into the device pins. This surge current can inject high-frequency switching noise into power planes of the printed circuit board

•Place high-current components near the power sources

•Do not share the same physical components (such as buffers and inverters) between high-speed and low-speed signals. Use separate parts.

•Place clock drivers and receivers such that clock trace length is minimized

•Place clock generation circuits near a ground stitch location. Place a localized ground plane around the clock circuits and connect the localized plane to system ground plane

•Install clock circuits directly on the printed circuit board, not on sockets

•Clock crystals should lie flat against the board to provide better coupling of electromagnetic fields to the board

4.5Stack-Up Selection

Stack-up selection directly affects the trace geometry which, in turn, affects the characteristic impedance requirement for the printed-circuit board. Additionally, the clean, noise-free-planes design and placement is significantly important as components run at higher speeds requiring more power.

Considerations include:

•Low-speed, printed-circuit-board construction — for example two-layer boards:

—Advantages:

•Inexpensive

•Manufactured by virtually all printed-circuit-board vendors

—Disadvantages:

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	57

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §