Intel IXP43X manual HSS Interface, Device Connection

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Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

3.8.2Device Connection

The following example shown in Figure 10 shows a typical interface to an ADSL Framer via the UTOPIA bus. Notice that depending on the framer used some control signals might be required which can be derived from the Expansion bus or the GPIO signals.

Figure 10. UTOPIA Interface Example

Intel® IXP43X
Product Line of
Network
Processors	Control Signals
EX_BUS	Control Signals
EX_BUS
			Analog Front
ATM Layer Device	25 MHz	ADSL Framer	End
		Multi-Channel	AFE	RJ11
UTP_OP_CLK		TXCLK
UTP_OP_FCO		TXENB#
UTP_OP_ADDR[4:0]		TXADDR[4:0]
UTP_OP_FCI		TXCLAV
UTP_OP_SOC		TXSOC
UTP_OP_DATA[7:0]		TXDATA[7:0]
UTP_IP_FCO		RXENB#
UTP_IP_ADDR[4:0]		RXADDR[4:0]
UTP_IP_FCI		RXCLAV
UTP_IP_SOC		RXSOC
UTP_IP_DATA[7:0]		RXDATA[7:0]	AFE	RJ11
UTP_IP_CLK		RXCLK	AFE	RJ11
UTP_IP_CLK		RXCLK
UTOPIA Level 2
Interface	25 MHz
	25 MHz	SDRAM
		SDRAM
		Local Memory
				B4107 -005

3.9HSS Interface

NPE A has an integrated High-Speed Serial (HSS) module, whose primary function is to provide connectivity between the internal NPE A and the external HSS interface. There is one HSS port that can directly interface to SLIC/CODEC devices for voice applications, or serial DSL framers. The HSS ports are software configurable to support various serial protocols, such as T1/ E1/J1, and MVIP. For a list of supported protocols, see the Intel® IXP400 Software Programmer’s Guide.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	41

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio InterfaceDesign Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsCrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §