Intel IXP43X manual Good Design Practice for VIA Hole Placement

Page 62

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 20. Good Design Practice for VIA Hole Placement

25 mils min

25 mils min

25 mils min

B2266-01

Figure 20 and Figure 21 show good and poor design practices for via placement on surface-mount boards.

Figure 22 shows minimum pad-to-pad clearance for surface-mount passive components and PGA or BGA components.

Figure 21. Poor Design Practice for VIA Placement

Flush Via min

Potential Bridge min

B2267-01

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

62

Document Number: 316844; Revision: 001US

Page 61 Page 63
Image 62
Page 61 Page 63
Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name DescriptionList of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol DescriptionDDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately EthernetType Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface ExampleDesign Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPADDR40 UTPOPDATA4UTPOPDATA75 UtpopfciUtpipsoc ClavUtpipfci ETHARXDATA30 EtharxclkUTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40HSS Interface Device ConnectionHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 PciclkinPCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection FieldPCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling§ § General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGACrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDrasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / DdrcasnDDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations SizeaAddress Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsTiming Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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