Intel IXP43X manual DDRII/I Sdram Interface, Soft Fusible Features Sheet 2, Ethernet, Ddr Ecc

Page 18

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 3.

Soft Fusible Features (Sheet 2 of 2)

 

 

 

 

Name

Description

 

 

 

 

ETHERNET

Can enable MII MACs. Enable of MACs can be separately done per each NPE.

 

 

 

 

USB Host

Each USB can be Enable separately.

 

 

 

 

DDR ECC

ECC can be enabled or disabled separately from the rest of the DDR interface.

 

 

 

3.2 DDRII/I SDRAM Interface

The IXP43X network processors support unbuffered, DDRI-266 or DDRII-400 SDRAM technology, capable of addressing two memory banks (one bank per CS). Each bank can be configured to support 32/64/128/256/512-Mbyte for a total combined memory support of 1 Gbyte.

The IXP43X network processors integrate a high-performance, multi-ported Memory Controller Unit (MCU) to provide a direct interface with its local memory subsystem. The MCU supports:

•DDR II/I or DDRII-400 SDRAM

•128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support

•Supports 256/512-Mbit technologies for the DDRII-400

•Only unbuffered DRAM support (No registered DRAM support)

•Dedicated port for Intel XScale processor to the DDRII/DDRI SDRAM

•Between 32 MBs and 1-GB of 32-bit DDRI SDRAM

•Between 64MBs and 512 MBs of 32-bit DDRII SDRAM

•16MB for 16-bit memory systems for DDRI SDRAM (non-ECC) supporting 128-Mbit technology only

•32MB for 16-bit memory systems for DDRII SDRAM (non-ECC) supporting 256-Mbit technology only

•Single-bit error correction, multi-bit detection support (ECC)

•32-bit, 40-bit wide memory interfaces (non-ECC and ECC support), and 16-bit wide memory interfaces (non-ECC)

The DDRII/DDRI SDRAM interface provides a direct connection to a high-bandwidth and reliable memory subsystem. The DDRII/DDRI SDRAM interface is a 16 or 32-bit-wide data path.

The device supports non-ECC and ECC for error correction, which can be enable or disable by software as required. Banks have a bus width of 32 bits for non ECC or 40 bits for ECC enable (32-bit data + 8-bit ECC).

An 8-bit Error Correction Code (ECC) across each 32-bit word improves system reliability. It is important to note that ECC is also referred to as CB in many DIMM specifications. The pins on the IXP43X network processors are called DDR_CB[7:0]. ECC is only implemented in the 32-bit mode of operation, while the algorithm used to generate the 8-bit ECC is implemented over 64-bit.

The ECC circuitry is designed to operate always on a 64-bit data and when operating in 32-bit mode, the upper 32 bits are driven to zeros internally. To summarize the impact to the customer, the full 8 bits of ECC is stored and read from a memory array for the ECC logic to work. An 8-bit-wide memory is used when implementing ECC.

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

18

Document Number: 316844; Revision: 001US

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Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Content Overview Chapter Name DescriptionList of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol DescriptionDDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately EthernetType Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII Gpio Interface MII Interface ExampleGpio Signal Recommendations USB InterfaceDesign Notes USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPADDR40 UTPOPDATA4UTPOPDATA75 UtpopfciUtpipsoc ClavUtpipfci ETHARXDATA30 EtharxclkUTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40HSS Interface Device ConnectionHSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 PciclkinPCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection FieldPCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Input System Clock Clock SignalsClock Signals Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling§ § General Recommendations Component PlacementPCB Overview Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDrasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / DdrcasnDDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations SizeaAddress Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsTiming Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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