Intel IXP43X manual UTPIPDATA5, UTPIPDATA6, UTPIPDATA7, UTPIPADDR40, Rxenbn, Utpipfco

Page 40

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

 

 

Type

Pull

 

 

Name

Up/

Description

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 input data. Also known as RX_DATA.

 

 

 

 

Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

 

 

 

 

PHY.

 

 

 

 

• When an NPE A is configured in UTOPIA Level 2 mode of operation and the

UTP_IP_DATA[5] /

 

 

signal is not used, it should be pulled high through a 10-KΩresistor.

I

Yes

MII Mode of Operation:

ETHA_COL

Asserted by the PHY when a collision is detected by the PHY.

 

 

 

 

 

 

• When an NPE A is configured in MII mode of operation and the signal is not

 

 

 

 

used, it should be pulled low through a 10-KΩresistor.

 

 

 

 

When this interface is disabled through the UTOPIA Level 2 and/ or the NPE-A

 

 

 

 

Ethernet soft fuse and is not being used in a system design, it is not required for

 

 

 

 

any connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 input data. Also known as RX_DATA.

 

 

 

 

Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

 

 

 

 

PHY.

 

 

 

 

MII Mode of Operation:

UTP_IP_DATA[6] /

 

 

Asserted by the PHY when transmit medium or receive medium is active. De-

I

Yes

asserted when both the transmit and receive medium are idle. Remains asserted

ETHA_CRS

throughout the duration of collision condition. PHY asserts CRS asynchronously

 

 

 

 

 

 

and de-asserts synchronously with respect to ETHA_RXCLK.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Mode of Operation:

 

 

 

 

UTOPIA Level 2 input data. Also known as RX_DATA.

 

 

 

 

Used by the processor to receive data from an ATM UTOPIA Level 2-compliant

 

 

 

 

PHY.

 

 

 

 

MII Mode of Operation:

UTP_IP_DATA[7]

I

Yes

Not Used.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor. When this

 

 

 

 

interface is disabled through the UTOPIA Level 2 and/or the NPE-A Ethernet soft

 

 

 

 

fuse and is not being used in a system design, it is not required for any

 

 

 

 

connection. Refer to Expansion Bus Controller chapter of the Intel® IXP43X

 

 

 

 

Product Line of Network Processors Developer’s Manual.

 

 

 

 

 

 

 

 

 

Receive PHY address bus.

UTP_IP_ADDR[4:0]

I/O

No

Used by the processor while operating in an MPHY mode to poll and select a

 

 

 

 

single PHY at any given point of time.

 

 

 

 

 

 

 

 

 

UTOPIA Level 2 Input Data Flow Control Output signal: Also known as the

 

 

 

 

RX_ENB_N.

 

 

 

 

In a SPHY configuration, UTP_IP_FCO is used to inform the PHY that the

 

 

 

 

processor is ready to accept data.

UTP_IP_FCO

TRI

Yes

In MPHY configurations, UTP_IP_FCO is used to select those PHY drives that

signals UTP_RX_DATA and UTP_RX_SOC. The PHY is selected by placing the

 

 

 

 

PHY’s address on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during

 

 

 

 

the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next

 

 

 

 

clock cycle.

 

 

 

 

When this interface/signal is enabled and is not being used in a system design,

 

 

 

 

the interface/signal should be pulled high with a 10-KΩresistor.

 

 

 

 

 

††

Refer to the Intel® IXP43X Product Line of Network Processors Developer’s Manual for information on how to select an

 

interface.

 

 

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

40

Document Number: 316844; Revision: 001US

Page 39 Page 41
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Page 39 Page 41
Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesHDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Content Overview Chapter Name DescriptionRelated Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol DescriptionSoft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface EthernetSignal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII Gpio Interface MII Interface ExampleUSB Interface Gpio Signal RecommendationsDesign Notes USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA4 UTPOPDATA75UTPOPADDR40 UtpopfciClav UtpipfciUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40HSS Interface Device ConnectionHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan PciclkinConnect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldOn the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling§ § Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAUSB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaSupported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement BanksDdrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsDDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer StackupGroup Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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