Intel IXP43X manual Device Connection, MII, MII NPE C Signal Recommendations Sheet 2

Page 31

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 10.

MII NPE C Signal Recommendations (Sheet 2 of 2)

 

 

 

 

 

 

 

 

 

 

Name

 

 

Type

Pull

 

 

 

 

 

Up/

Recommendations

 

 

 

 

Field

 

 

 

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Externally supplied receive clock:

 

 

 

 

 

 

 

• 25 MHz for 100 Mbps operation

 

ETHC_rxclk

 

 

I

Yes

• 2.5 MHz for 10 Mbps

 

 

 

 

 

 

 

This MAC contains hardware hashing capabilities that are local to the interface.

 

 

 

 

 

 

 

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Receive data bus from PHY, data sampled synchronously, with respect to ETHC_RXCLK.

 

ETHC_rxdATA[3:0]

 

I

Yes

This MAC contains hardware hashing capabilities that are local to the interface.

 

 

 

 

 

 

 

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Receive data valid is used to inform the MII interface about data that is being sent by

 

ETHC_rxdv

 

 

I

Yes

the Ethernet PHY

 

 

 

This MAC contains hardware hashing capabilities that are local to the interface.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asserted by the PHY when a collision is detected by the PHY. This MAC contains

 

 

 

 

 

 

 

hardware hashing capabilities that are local to the interface.

 

ETHC_col

 

 

I

Yes

Should be pulled high through a 10-KΩresistor when not being utilized in the system

 

 

 

When this interface is disabled through the NPE-C Ethernet soft fuse (refer to the

 

 

 

 

 

 

 

Expansion Bus Controller chapter of the Intel® IXP43X Product Line of Network

 

 

 

 

 

 

 

Processors Developer’s Manual) and is not being used a system design, this interface/

 

 

 

 

 

 

 

signal is not required for any connection.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Asserted by the PHY when the transmit medium or receive medium are active.

 

 

 

 

 

 

 

De-asserted when both the transmit and receive medium are idle. Remains asserted

 

ETHC_crs

 

 

I

Yes

throughout the duration of collision condition. PHY asserts CRS asynchronously and

 

 

 

de-asserts synchronously with respect to ETHC_RXCLK.

 

 

 

 

 

 

 

This MAC contains hardware hashing capabilities that are local to the interface.

 

 

 

 

 

 

 

Should be pulled high through a 10-KΩresistor when not being utilized in the system.

 

 

 

 

 

 

 

 

 

Notes:

 

 

 

 

 

 

 

1.

Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after

 

 

being disabled without asserting a system reset.

 

2.

Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left

 

 

unconnected.

 

 

 

 

3.

Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in note 1 — only require

 

 

pull-ups or pull-downs in the clock-input signals.

 

 

 

 

 

 

 

 

Table 11.

MAC Management Signal Recommendations - NPE A and NPE C

 

 

 

 

 

 

Name

Type

Pull

 

 

Up/

Recommendations

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NPE A and NPE C

 

 

 

 

Management data input output. Provides the write data to both PHY devices connected to

 

ETH_mdio

IO

Yes

each MII interface. An external pull-up resistor of 1.5K ohm is required on

 

ETHC_MDIO to properly quantify the external PHYs used in the system. For specific

 

 

 

 

 

 

 

 

implementation, see the IEEE 802.3 specification.

 

 

 

 

Should be pulled high through a 10-KΩresistor when not being utilized in the system

 

 

 

 

 

 

 

 

 

NPE A and NPE C

 

ETH_mdc

O

No

Management data clock. Management data interface clock is used to clock the MDIO signal as

 

an output and sample the MDIO as an input. The ETHC_MDC is an input on power up and can

 

 

 

 

be configured to be an output through Intel APIs documented in the Intel® IXP400 Software

 

 

 

 

Programmer’s Guide

 

 

 

 

 

3.5.2Device Connection, MII

Figure 6 is a typical example of an Ethernet PHY device interfacing to one of the MACs via the MII hardware protocol.

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

31

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsHDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Chapter Name Description Content OverviewTerm Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1List of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram InterfaceName Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 TypeDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceMII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII MII Interface Example Gpio InterfaceUSB Interface Gpio Signal RecommendationsDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40ETHARXDATA30 Etharxclk ClavUtpipfci UtpipsocUTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7Device Connection HSS InterfaceHSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 PciintanType Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2PCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Oscillator Clock SignalsClock Signals Input System ClockRecommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations§ § Component Selection Component PlacementPCB Overview General RecommendationsStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsUSB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHzPCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramDcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / DdrrasnDDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram ConfigurationsTechnology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select TotalDdrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsPrinted Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing RelationshipsGroup Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §
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