Intel IXP43X manual Expansion Bus Signal Recommendations Sheet 1

Page 21

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

3.3Expansion Bus

The Expansion Bus of the IXP43X network processors is specifically designed for compatibility with Intel-and Motorola* style microprocessor interfaces.

The expansion bus controller includes a 24-bit address bus and a 16-bit wide data path, running at a maximum speed of 80 MHz from an external clock oscillator. The bus can be configure to support the following target devices:

•

Intel multiplexed

•

Intel non-multiplexed

•

Intel StrataFlash®

•

Synchronous Intel StrataFlash® Memory

•

Motorola non multiplexed

•

Motorola multiplexed

The expansion bus controller also has an arbiter that supports up to four external devices that can master the expansion bus. External masters can be used to access external slave devices that reside on the expansion bus, including access to internal memory mapped regions within the IXP43X network processors.

All supported modes are seamless and no additional glue logic is required. Other cycle types can be supported by configuring the Timing and Control Register for Chip Select.

The expansion interface functions support 8-bit or 16-bit data operation and allows an address range of 512 bytes to 16 MBs, using 24 address lines for each of the four independent chip selects.

Access to the expansion-bus interface is completed in five phases. Each of the five phases can be lengthened or shortened by setting various configuration registers on a per-chip-select basis. This feature allows the IXP43X network processors to connect to a wide variety of peripheral devices with varying speeds.The expansion interface supports Intel or Motorola* microprocessor style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the four chip-selects.

The expansion interface is an asynchronous interface to externally connected chips. A clock is supplied to the IXP43X network processors expansion interface for the interface to operate. This clock can be driven from GPIO 15 or an external source. Devices on the expansion bus can be clocked by an external clock at a rate of up to 80 MHz. If GPIO 15 is used as the clock source, the Expansion Bus interface can only be clocked at a maximum of 33.33 MHz. GPIO 15’s maximum clock rate is 33.33 MHz.

3.3.1Signal Interface

Table 5.

Expansion Bus Signal Recommendations (Sheet 1 of 2)

 

 

 

 

 

 

 

Type

Pull

 

Name

 

Up

Recommendations

 

Field

 

 

Down

 

 

 

 

 

 

 

 

 

 

EX_CLK

 

I

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_ALE

 

TRI O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

 

 

 

 

Use 470Ω resistors for pull-downs; required for boot strapping for initial configuration of

 

 

 

 

Configuration Register 0. Pull-ups are not required as for when the system comes out of

EX_ADDR[23:0]

 

I/O

Yes

reset, all bits are initially set HIGH. For more details, see Table 6.

 

 

 

 

For additional details on address strapping, see the Intel® IXP43X Product Line of Network

 

 

 

 

Processors Developer’s Manual.

 

 

 

 

 

EX_WR_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

EX_RD_N

 

I/O

No

Use series termination resistor, 10Ω to 33Ω at the source.

 

 

 

 

 

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

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Contents Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content OverviewAcronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term ExplanationList of Acronyms and Abbreviations Sheet 2 OverviewHDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture DescriptionIntel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol DescriptionUSB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface EthernetDDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram InitializationExpansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface 16-Bit Device Interface Flash InterfaceFlash Interface Example Uart InterfaceUart Signal Recommendations Uart Interface Example MII InterfaceSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio InterfaceGpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal RecommendationsCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 UtpopfciUtpipfci ClavUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40Device Connection HSS InterfaceHSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0HSS Interface Example SSP InterfaceSynchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI InterfacePCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan PciclkinPCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldSignal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldPCI Host/Option Interface Pin Description Sheet 3 Jtag InterfaceClock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling§ § PCB Overview Component PlacementGeneral Recommendations Component SelectionStack-Up Selection Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing GuideGeneral Component Spacing Signal Changing Reference PlanesGood Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal ConsiderationsMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length LimitsRouting Guidelines Signal LoadingIntroduction Ddrii / Ddri SdramGroup Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3Parameter Definition Data and Control GroupsDCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing GuidelinesSignal Group Members Ddrii Command Signal Group Routing Guidelines§ §
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