Intel IXP43X manual General Layout and Routing Guide, General Layout Guidelines

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

5.0General Layout and Routing Guide

5.1Overview

This chapter provides routing and layout guides for hardware and systems based on the IXP43X network processors.

The high-speed clocking required when designing with the processors requires special attention to signal integrity. In fact, it is highly recommended that the board design be simulated to determine optimum layout for signal integrity. The information in this chapter provides guidelines to aid designers with board layout. In cases where it is too difficult to follow a design rule, engineering judgment must be used.

5.2General Layout Guidelines

The layout guidelines recommended in this section are based on experience and knowledge gained from previous designs. Layer stacking varies, depending on design complexity, however following standard rules helps minimize potential problems dealing with signal integrity.

The following recommendations help to route a functional board:

•Provide enough routing layers to comply with minimum and maximum timing requirements of the IXP43X network processors and other components.

•Connectors, and mounting holes must be placed in a ways that will not interfere with basic design guidelines in this document.

•Provide uniform impedance throughout the board, specially for high speed areas such us clocking, DDRII/I-SDRAM, PCI, device bus, and so forth.

•Place analog, high-voltage, power supply, low-speed, and high-speed devices in various sections of the board.

•Decoupling capacitors must be placed next to power pins.

•Series termination resistors must be placed close to the source.

•Analog and digital sections of the board must be physically isolated from each other. No common ground, power planes, and signal traces are allowed to cross-isolation zones. Use appropriately sized PCB traces for larger enough to handle peak current. Keep away from high-speed digital signals.

•Keep stubs as short as possible (preferably, the electrical length of the stub less than half of the length of the rise time of signal).

•All critical signals should be routed before all other non-critical signals.

•Do not route signals close to the edge of the board, power or ground planes. Route signal at least 50 to 100 mils away from the edge of the plane.

•Try to match buses to the same trace length and keep them in groups adjacent to each other, away from other signals.

•Route processor address, data and control signals using a daisy-chaintopology.

•Minimize number of vias and corners on all high speed signals.

•Do not route under crystals or clock oscillators, clock synthesizers, or magnetic devices (ferrites, toroids).

•Maintain trace spacing consistent between differential pairs and match trace length.

•Keep differential signals away from long and parallel, high-speed paths, such as clock signals and data strobe signals.

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

60

Document Number: 316844; Revision: 001US

Page 59 Page 61
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Page 59 Page 61
Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Content Overview Chapter Name DescriptionRelated Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol DescriptionSoft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface EthernetSignal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleSignal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII Gpio Interface MII Interface ExampleGpio Signal Recommendations USB InterfaceDesign Notes USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA4 UTPOPDATA75UTPOPADDR40 UtpopfciClav UtpipfciUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40HSS Interface Device ConnectionHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan PciclkinConnect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldOn the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling§ § Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGAMII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecClock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaSupported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement BanksDDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsDDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer StackupSignal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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