Intel IXP43X manual DDRII/I Sdram Initialization, DDRII/I Sdram Interface Pin Description Sheet 2

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Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 4.

DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2)

 

 

 

 

 

 

 

 

Type

 

VTT

 

Name

 

Device-Pin Connection

Terminatio

Description

 

Field

 

 

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ECC Bus — Eight-bit error correction code

 

 

 

 

 

which accompanies the data on D_DQ[31:0]/

D_CB[7:0] /

 

I/O

Connect to ECC memory devices.

Yes

DDR_DQ[31:0].

DDR_CB[7:0]

 

When ECC is disabled and not being used in a

 

 

 

 

 

 

 

 

 

system design, these signals can be left un-

 

 

 

 

 

connected.

 

 

 

 

 

 

 

 

 

 

 

Data Strobes Differential — Strobes that

 

 

 

 

 

accompany the data to be read or written from

 

 

 

Connect DQS[3:0] to devices with

 

the DDRII/I SDRAM devices. Data is sampled

D_DQS[4:0] /

 

 

 

on the negative and positive edges of these

 

I/O

data signals and DQS[4] to

Yes

DDR_DQS[4:0]

 

strobes. D_DQS[3:0]/DDR_DQS[3:0] are

 

 

devices with ECC signals.

 

 

 

 

 

intended to correspond to each byte of a word

 

 

 

 

 

 

 

 

 

 

of data. D_DQS[4]/DDR_DQS[4] is intended to

 

 

 

 

 

be utilized for the ECC byte of data.

 

 

 

 

 

 

 

 

 

 

 

Clock enables — One clock after D_CKE[1:0]/

 

 

 

 

 

DDR_CKE[1:0] is de-asserted, data is latched

 

 

 

Use one CKE per bank, never mix

 

on D_DQ[31:0]/DDR_DQ[31:0] and

D_CKE[1:0] /

 

 

 

D_CB[7:0]/DDR_CB[7:0]. Burst counters

 

O

the CKE on the same bank. Use

Yes

 

within DDRII/I SDRAM device are not

DDR_CKE[1:0]

 

CKE[0] for bank0 and CKE[1] for

 

 

 

incremented. De-asserting this signal places

 

 

 

bank1

 

 

 

 

 

the DDRII/I SDRAM in self-refresh mode. For

 

 

 

 

 

 

 

 

 

 

normal operation, D_CKE[1:0]/DDR_CKE[1:0]

 

 

 

 

 

must be asserted.

 

 

 

 

 

 

D_ODT[1:0]

 

 

 

 

On Die Termination Control — Turns on DDR II

 

 

 

 

SDRAM termination during writes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compensation for DDR OCD (analog) DDRII

D_RES[2:1]

 

 

Refer to Figure 27

 

mode only. This function is not enable and

 

 

 

 

 

special connection is required.

 

 

 

 

 

 

 

 

 

 

 

Compensation Voltage Reference (analog) for

D_SLWCRES

 

 

Refer to Figure 27

 

DDR driver slew rate control connected

 

 

 

 

 

through a resistor to D_CRES0.

 

 

 

 

 

 

 

 

 

 

 

Compensation Voltage Reference (analog) for

D_IMPCRES

 

 

Refer to Figure 27

 

DDR driver impedance control connected

 

 

 

 

 

through a resistor to D_CRES0.

 

 

 

 

 

 

 

 

 

 

 

Analog VSS Ref Pin (analog) both D_SLWCRES

 

 

 

 

 

and D_IMPCRES signals connect to this pin

 

 

 

 

 

through a reference resistor. For DDRII/I

 

 

 

 

 

respectively:

D_CRES0

 

O

Tied off to a resistor

Tied off to a

- 285 / 387Ohm Resistor connected to

 

resistor

DDR_IMPCRES used for process and

 

 

 

 

 

 

 

 

 

temperature adjustments.

 

 

 

 

 

- 825 / 845Ohm Resistor connected to

 

 

 

 

 

DDR_SLWCRES used for process and

 

 

 

 

 

temperature adjustments.

 

 

 

 

 

 

 

 

 

 

 

DDRII/IDDRII/I SDRAM Voltage Reference — is

D_VREF / DDR_VREF

I

VCCDDR/2

VCCDDR/2

used to supply the reference voltage to the

differential inputs of the memory controller

 

 

 

 

 

pins.

 

 

 

 

 

 

3.2.2DDRII/I SDRAM Initialization

For instructions on DDRII/I SDRAM initialization, refer to DDR SDRAM Initialization subsection in the Memory Controller chapter of the Intel® IXP43X Product Line of Network Processors Developer’s Manual.

Intel® IXP43X Product Line of Network Processors

 

HDG

April 2007

20

Document Number: 316844; Revision: 001US

Page 19 Page 21
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Contents Intel IXP43X Product Line of Network Processors Hardware Design GuidelinesApril Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name DescriptionRelated Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term ExplanationOverview List of Acronyms and Abbreviations Sheet 2HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory MapIntel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol DescriptionSoft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface EthernetSignal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description FieldDDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field DownBoot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz4 16-Bit Device Interface Flash Interface 16-Bit Device InterfaceUart Interface Flash Interface ExampleUart Signal Recommendations MII Interface Uart Interface ExampleMII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface ExampleDesign Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field DownCommon Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPDATA4 UTPOPDATA75UTPOPADDR40 UtpopfciClav UtpipfciUtpipsoc ETHARXDATA30 EtharxclkUTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40HSS Interface Device ConnectionHigh-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0SSP Interface HSS Interface ExampleSynchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface ExamplePCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan PciclkinConnect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection FieldOn the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description FieldJtag Interface PCI Host/Option Interface Pin Description Sheet 3Clock Signals Clock SignalsInput System Clock Clock OscillatorRecommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling§ § Component Placement PCB OverviewGeneral Recommendations Component SelectionComponent Placement on a PCB Stack-Up SelectionControlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout GuidelinesSignal Changing Reference Planes General Component SpacingGood Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGACrosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSecParameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing GuidelinesSignal Loading Routing GuidelinesDdrii / Ddri Sdram IntroductionDDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / DdrcasnDDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations SizeaSupported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement BanksDDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum UnitsDDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer StackupTiming Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock GroupData and Control Groups Parameter DefinitionDdrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310Ddrii Command Signal Group Routing Guidelines Signal Group Members§ §
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