Intel IXP43X manual Signal Interface, DDRII/I Sdram Interface Pin Description Sheet 1, Type

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

The memory controller only corrects single bit ECC errors on read cycles. The ECC is stored into the DDRII/DDRI SDRAM array along with the data and is checked when the data is read. If the code is incorrect, the MCU corrects the data before reaching the initiator of the read. ECC error scrubbing is done with software. User-defined fault correction software is responsible for The value written back into the memory location contains the 32-bit word with the modified byte and the new ECC value.

Refer to the Intel® IXP43X Product Line of Network Processors Datasheet for a detailed list of features.

General DDRII/I SDRAM routing guidelines can be found in Section 7.3.3, “Routing Guidelines” on page 82. For more detailed information, see the PC266 and PC400 DDR SDRAM specification.

3.2.1Signal Interface

Table 4.	DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)
		Type		VTT
Name			Device-Pin Connection	Terminatio	Description
		Field
				n
			Connect a pair of differential clock
D_CK[2:0] /		O	signals to every device; When		DDRII/I SDRAM Clock Out — Provides the
			using both banks, daisy chain	No	positive differential clocks to the external
DDR_CK[2:0]
			devices with same data bit		SDRAM memory subsystem.
			sequence.
D_CK_N[2:0] /					DDRII/I SDRAM Clock Out — Provides the
		O	Same as above	No	negative differential clocks to the external
DDR_CK_N[2:0]
					SDRAM memory subsystem.
D_CS_N[1:0] /			Use the same CS to control 32-bit		Chip Select — Must be asserted for all
		O		Yes	transactions to the DDRII/I SDRAM device.
C_CS_N[1:0]			data + 8-bit ECC, per bank
					One per bank.
D_RAS_N /			The RAS signal must be connected		Row Address Strobe — Indicates that the
		O	to each device in a daisy chain	Yes	current address on D_MA[13:0] /
DDR_RAS_N
			manner		DDR_MA[13:0] is the row.
D_CAS_N /			The CAS signal must be connected		Column Address Strobe — Indicates that the
		O	to each device in a daisy chain	Yes	current address on D_MA[13:0] /
DDR_CAS_N
			manner		DDR_MA[13:0] is the column.
			The WE signal must be connected		Write Strobe — Defines whether or not the
D_WE_N / DDR_WE_N		O	to each device in a daisy chain	Yes	current operation by the DDRII/I SDRAM is to
			manner		be a read or a write.
					Data Bus Mask — Controls the DDRII/I SDRAM
			Connect to each DM device pin.		data input buffers. Asserting D_WE_N/
					DDR_WE_N causes the data on D_DQ[31:0]/
			For the 8-bit devices connect one		DDR_DQ[31:0] and D_CB[7:0]/DDR_CB[7:0]
D_DM[4:0] /			DM signal per device.		to be written into the DDRII/I SDRAM devices.
		O	For the 16-bit devices connect two	Yes	D_DM[4:0]/DDR_DM[4:0] controls this
DDR_DM[4:0]
			DM signal per device (depending		operation on a per-byte basis. D_DM[3:0]/
			on how many data bits are being		DDR_DM[3:0] are intended to correspond to
			used).		each byte of a word of data. D/DM[4]/
					DDR_DM[4] is intended to be utilized for the
					ECC byte of data.
D_BA[1:0] /			The BA signals must be connected		DDRII/I SDRAM Bank Selects — Controls which
					of the internal DDRII/I SDRAM banks to read
		O	to each device in a daisy chain	Yes
DDR_BA[1:0]					or write. D_BA[1:0]/DDR_BA[1:0] are used for
			manner.
					all technology types supported.
D_MA[13:0] /			All address signals must be		Address bits 13 through 0 — Indicates the row
					or column to access depending on the state of
		O	connected to each device in a	Yes
DDR_MA[13:0]					D_RAS_N/DDR_RAS_N and D_CAS_N/
			daisy chain manner.
					DDR_CAS_N.
D_DQ[31:0] /		I/O	Must be connected in parallel to	Yes	Data Bus — 32-bit wide data bus.
DDR_DQ[31:0]			achieve a 32-bit bus width.
				Intel® IXP43X Product Line of Network Processors
April 2007					HDG
Document Number: 316844; Revision: 001US					19