LSI 53C810A technical manual PCI Bus Interface Signals, System Signals

4.1 PCI Bus Interface Signals

The PCI signal definitions are organized into the following functional groups: Power and Ground Signals, System Signals, Address and Data Signals, Interface Control Signals, Arbitration Signals, and Error Reporting Signals.

4.1.1 System Signals

Table 4.2 describes the System Signals group.

Table 4.2		System Signals
Name	Pin No.		Type	Description
CLK	80		I	Clock provides timing for all transactions on the PCI bus and is an input to
				every PCI device. All other PCI signals are sampled on the rising edge of
				CLK, and other timing parameters are defined with respect to this edge.
				Clock can optionally serve as the SCSI core clock, but this may effect fast
				SCSI transfer rates.
RST/	79		I	Reset forces the PCI sequencer of each device to a known state. All T/S
				and S/T/S signals are forced to a high impedance state, and all internal logic
				is reset. The RST/ input is synchronized internally to the rising edge of CLK.
				The CLK input must be active while RST/ is active to properly reset the
				device.

PCI Bus Interface Signals 4-5