Register 0x21 0xA1, Chip Test Four CTEST4 Read/Write | LSI 53C810A

when an interrupt occurs. These bits are unstable while data is being transferred between the two cores; once the chip has stopped transferring data, these bits are stable.

The DMA FIFO (DFIFO) register counts the number of bytes transferred between the DMA core and the SCSI core. The DMA Byte Counter (DBC) register counts the number of bytes transferred across the host bus. The difference between these two counters represents the number of bytes remaining in the DMA FIFO.

The following steps determine how many bytes are left in the DMA FIFO when an error occurs, regardless of the transfer direction:

1.Subtract the seven least signiﬁcant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register.

2.AND the result with 0x7F for a byte count between zero and 64.

Note: To calculate the total number of bytes in both the DMA FIFO and SCSI logic, see Section 2.5.1.1, “Data Paths,” in Chapter 2, “Functional Description.”

Register: 0x21 (0xA1)

Chip Test Four (CTEST4)

Read/Write

7	6	5	4	3	2		0
BDIS	ZMOD	ZSD	SRTM	MPEE		FBL[2:0]

0	0	0	0	0	0	0	0

BDIS	Burst Disable						7

When set, this bit causes the LSI53C810A to perform back-to-back cycles for all transfers. When this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. The handling of opcode fetches is dependent on the setting of the Burst Opcode Fetch bit in the DMA Mode (DMODE) register.

5-34	Operating Registers

Image 108

LSI 53C810A technical manual Register 0x21 0xA1, Chip Test Four CTEST4 Read/Write, Bdis, Burst Disable

Contents

Technical Manual R c h 2 0 0 Trademark Acknowledgment Audience Organization Ansi PCI Special Interest Group Conventions Used in This ManualRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology LSI53C810A Beneﬁts Summary Scsi Performance PCI Performance IntegrationEase of Use Flexibility Reliability Testability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Chapter Functional Description Scsi Core Scripts Processor DMA Core Sdms Software The Total Scsi Solution Prefetching Scripts Instructions PCI Cache Mode Opcode Fetch Burst Capability Loopback Mode Parity OptionsLoad and Store Instructions 2 3.3 V/5 V PCI Interface Bits Used for Parity Control and Observation BIt Name Location Description Scsi Parity Errors and Interrupts Scsi Parity Control DMA Fifo Data Paths Asynchronous Scsi Send Synchronous Scsi SendAsynchronous Scsi Receive Synchronous Scsi Receive LSI53C810A Host Interface Data Paths Scsi Bus Interface Terminator NetworksSelect/Reselect During Selection/Reselection Active or Regulated Termination Synchronous Operation Determining the Data Transfer RateSCNTL3 Register, Bits 64 SCF20 SCNTL3 Register, Bits 20 CCF20 Sxfer Register, Bits 75 TP20Achieving Optimal Scsi Send Rates Interrupt Handling Polling and Hardware Interrupts Registers Interrupt Handling Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Istat Functional Description PCI Addressing 1 Conﬁguration Space PCI Bus Commands and Functions Supported 2.1 I/O Read Command2.2 I/O Write Command Support for PCI Cache Line Size Register Selection of Cache Line Size AlignmentMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands PCI Bus Commands and Encoding Types Conﬁguration Registers PCI Conﬁguration Register Map Register Eper WIEEBM EMS EISEnable I/O Space0 Status Read/WriteDPE SSE RTA DPRData Parity Reported8 Register 0x08 Register 0x09RID Latency Timer Read/Write LTLatency Timer70 Register 0x0CRegister 0x0D Cache Line Size Read/Write Register 0x0E Register 0x10Register 0x14 Barz Register 0x3C Register 0x3DInterrupt Line Read/Write ILInterrupt Line70 Interrupt Pin Read Only IPInterrupt Pin70 Register 0x3E Register 0x3FMinGnt Read Only MGMinGnt70 MaxLat Read Only MLMaxLat70 PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Signals are assigned a type. There are four signal types Power and Ground Signals Functional Signal Grouping PCI Bus Interface Signals System SignalsSystem Signals Address and Data Signals Address and Data Signals Interface Control Signals Interface Control Signals Arbitration Signals Error Reporting SignalsArbitration Signals Error Reporting Signals Scsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface Signals MAC Signal Descriptions Chapter Operating Registers Register 0x00 Scsi Control Zero SCNTL0 Read/Write ARB10 Arbitration Mode Bits 1 Simple ArbitrationFull Arbitration, Selection/Reselection Start Start SequenceWatn Select with SATN/ on a Start Sequence4 EPC AAPTRG Register 0x01 EXCADB DHP CON RSTAesp Iarb SSTStart Scsi Transfer0 Register 0x02 Register 0x03SDU Reserved CCF20 Clock Conversion Factor Register 0x04 RRESRE Register 0x05 Reserved ENC20 Encoded LSI53C810A Chip Scsi IDScsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer Period75 TP2 TP1 TP0 Xferp Reserved MO30 Max Scsi Synchronous Offset Sclk SCNTL3 Register 0x06 Scsi Synchronous Offset ValuesScsi Destination ID Sdid Read/Write Reserved ENC20 Encoded destination Scsi ID Register 0x07 General Purpose Gpreg Read/WriteReserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write REQ ACKBSY SEL Register 0x0A 0x8A Scsi Selector ID Ssid Read OnlyVAL Scsi Valid Bit Register 0x0B 0x8B Register 0x0C 0x8C DFE MdpeAbrt SSI Register 0x0D 0x8D IIDILF ORF OLF AIPLOA WOA Register 0x0E 0x8E Scsi Status One SSTAT1 Read OnlyFF30 Fifo Flags Sdpl Latched Scsi Parity3 Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ Signal Register 0x0F 0x8FScsi Status Two SSTAT2 Read Only Ldsc Registers 0x10-0x13 DSA Srst SigpSEM Intf Interrupt-on-the-FlySipscsi Interrupt Pending1 Register 0x18 Dipdma Interrupt Pending0Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70 Register 0x19 Register 0x1A 0x9ADdir CIO TeopDreq Dack Register 0x1B 0x9B FLFCLF Registers 0x1C-0x1F 0x9C-0x9F Register 0x20 0xA0Temp DMA Fifo Dfifo Burst Disable Register 0x21 0xA1Chip Test Four CTEST4 Read/Write Bdis Zmod ZSDSrtm Register 0x22 0xA2 AdckBbck Register 0x23 0xA3 MasrChip Test Six CTEST6 Read/Write Dfdma FIFO70 Registers 0x24-0x26 0xA4-0xA6 DMA Byte Counter DBC Read/WriteDBC DMA Byte Counter 230 Register 0x27 0xA7 Registers 0x28-0x2B 0xA8-0xABRegisters 0x2C-0x2F 0xAC-0xAF Dnad Registers 0x30-0x33 0xB0-0xB3 DMA Scripts Pointer Save Dsps Read/WriteDsps DMA Scripts Pointer Save 310 Registers 0x34-0x37 0xB4-0xB7 Register 0x38 0xB8Scratcha Source I/O Memory Enable Destination I/O Memory EnableERLEnable Read Line3 Siom Burst Opcode Fetch Enable ErmpBOF MANManual Start Mode0 Register 0x39 0xB9 SIR Register 0x3A 0xBA Register 0x3B 0xBB SSM IrqmSTD Irqd Register 0x3C-0x3F 0xBC-0xBF COMAdder Sum Output Adder Read Only Adder Register 0x40 0xC0 CMPRSL SGE Scsi Reset Condition UDCUnexpected Disconnect PAR Register 0x41 0xC1 STOGEN HTH Initiator Mode Phase Mismatch Target Mode SATN/ Active Register 0x42 0xC2Scsi Interrupt Status Zero SIST0 Read Only CMPFunction Complete6 Transfer Sxfer register Parity Error Register 0x43 0xC3Scsi RST/ Received Scsi Interrupt Status One SIST1 Read Only Handshake-to-Handshake Timer Expired Register 0x44 0xC4Scsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70 Memory Access Control Macntl Read/Write Register 0x46 0xC6TYP30 Chip Type Register 0x47 0xC7 DWRDRD Pscpt Scsi Timer Zero STIME0 Read/Write HTH30 Handshake-to-Handshake Timer PeriodRegister 0x48 0xC8 GPIO0EN Scsi Timer One STIME1 Read/Write Reserved GEN30 General Purpose Timer PeriodRegister 0x49 0xC9 SELSelection Time-Out30 Register 0x4A 0xCA Response ID Respid Read/Write Respid Response ID70 Register 0x4C 0xCC SsaidSLT ART Register 0x4D 0xCD SclkSiso Register 0x4E 0xCE SCEROF SLB Register 0x4F 0xCF EXTLOW STR HSCDSI TTM Register 0x50 0xD0 Stwscsi Fifo Test Write0Scsi Input Data Latch Sidl Read Only Sidlscsi Input Data Latch150 Registers 0x54 0xD4 Registers 0x58 0xD8 Low Level Register Interface Mode Chapter Instruction Set Processor Scsi Scripts Sample Operation Scripts Instructions Instruction Set of the I/O Processor Block Move Instructions Scripts Overview First Dword IT10 Instruction Type Block Move 3130 Indirect AddressingDirect Addressing TIA Table Indirect Addressing Block Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 Second Dword TC230 Transfer Counter230Start Address 310 I/O Instruction IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 Reselect Instruction Disconnect Instruction Wait Select Instruction Set Instruction I/O Instruction Register Clear Instruction Select Instruction Wait Disconnect Instruction Wait Reselect Instruction Relative Addressing Mode TITable Indirect Mode25 Direct Table IndirectRelative Endid Set/Clear Sack Set/Clear SatnSAStart Address310 Read/Write Instructions Read-Modify-Write Cycles Move To/From Sfbr Cycles Read/Write Register Instruction Read/Write Instructions Byte Received Sfbr Transfer Control Instructions Jump Instruction Call Instruction Return Instruction Instruction Type Transfer Control Interrupt Instruction Interrupt on-the-Fly Instruction RARelative Addressing Mode23 Jump/Call an Absolute AddressJump/Call a Relative Address JMP Jump If True/False WVP DCM Jump Address 310 Memory Move Instructions Memory to Memory Move Instruction Third Dword No FlushTC230 Transfer Count Temp Register 310 Load and Store Instructions Read/Write System Memory from a Scripts Instruction IT20 Instruction Type 3129 DSA RelativeReserved 2726 No Flush Store instruction only This bit has no effect unless the Prefetch Enable bit DMA Control Dcntl register is set. For information onScripts instruction prefetching, see , Func Memory/IO Address / DSA Offset 310 Load and Store Instruction Format Chapter Electrical Characteristics DC Characteristics Absolute Maximum Stress Ratings Operating Conditions Scsi Signals-SD70/, SDP/, SREQ/, Sack Scsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, SrstInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signals-MAC/TESTOUT, REQ Output Signal-IRQCapacitance 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy DEVSEL/, STOP/, PERR/, PAR 11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER 12 TolerANT Technology Electrical Characteristics Pqfp Rise and Fall Time Test Conditions Input Current as a Function of Input Voltage AC Characteristics Clock Timing 14 Reset Input Timing Reset InputInterrupt Output PCI Interface Timing Diagrams Target TimingInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Interface Timing PCI Timing Scsi Timings 17 Initiator Asynchronous Send 5 Mbytes/s 18 Initiator Asynchronous Receive 5 Mbytes/s 20 Initiator Asynchronous Receive 19 Target Asynchronous Send 5 Mbytes/s 21 Target Asynchronous Send 20 Target Asynchronous Receive 5 Mbytes/s 22 Target Asynchronous Receive 21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings 24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Symbols Numerics IX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Reader’s Comments Excellent Good Average Fair Distributors by State California New York Direct Sales Representatives by State Component and Boards Sales Ofﬁces and Design Resource Centers International International Distributors