7.3 AC Characteristics

The AC characteristics described in this section apply over the entire range of operating conditions (refer to Section 7.1, “DC Characteristics”). Chip timings are based on simulation at worst case voltage, temperature, and processing. Timings were developed with a load capacitance of 50 pF. Table 7.13 and Figure 7.6 provide clock timing data.

Table 7.13

Clock Timing

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Max

Unit

 

 

 

 

 

t1

Bus clock cycle time

30

DC

ns

 

 

 

 

 

 

SCSI clock cycle time (SCLK)1

25

60

ns

 

 

 

 

 

t2

CLK LOW time2

12

ns

 

SCLK LOW time2

10

33

ns

 

 

 

 

 

t3

CLK HIGH time2

12

ns

 

SCLK HIGH time2

10

33

ns

t4

CLK slew rate

1

V/ns

 

SCLK slew rate

1

V/ns

 

 

 

 

 

1.This parameter must be met to ensure SCSI timings are within specification.

2.Duty cycle not to exceed 60/40.

Figure 7.6 Clock Timing

CLK, SCLK

t3

t1

t2

t4

7-10

Electrical Characteristics

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Image 192
LSI 53C810A technical manual AC Characteristics, Clock Timing