A SCSI gross error occurs

An unexpected disconnect occurs

A SCSI reset occurs

A parity error is detected

The handshake-to-handshake timer is expired

The general purpose timer is expired

To determine exactly which condition(s) caused the interrupt, read the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers.

DIPDMA Interrupt Pending0

This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C810A. The following conditions cause a DMA interrupt to occur:

A PCI parity error is detected

A bus fault is detected

An abort condition is detected

A SCRIPTS instruction is executed in single step mode

A SCRIPTS interrupt instruction is executed

An illegal instruction is detected

To determine exactly which condition(s) caused the interrupt, read the DMA Status (DSTAT) register.

Register: 0x18 (0x98)

Chip Test Zero (CTEST0)

Read/Write

7

0

FMT

1

1

1

1

1

1

1

1

FMTByte Empty in DMA FIFO[7:0]

This was a general purpose read/write register in previous LSI53C8XX family chips. Although it is still a read/write register, LSI Logic reserves the right to use these bits for future LSI53C8XX family enhancements.

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LSI 53C810A Register 0x18, Dipdma Interrupt Pending0, Chip Test Zero CTEST0 Read/Write, FMTByte Empty in DMA FIFO70