Selection of Cache Line Size, Alignment | LSI 53C810A instruction

3.2.2 Selection of Cache Line Size

The cache logic selects a cache line size based on the values for the burst size in the DMA Mode (DMODE) register and the PCI Cache Line Size register.

Note: The LSI53C810A does not automatically use the value in the PCI Cache Line Size register as the cache line size value. The chip scales the value of the Cache Line Size register down to the nearest binary burst size allowed by the chip (2, 4, 8 or 16), compares this value to the DMODE burst size, then selects the smallest as the value for the cache line size. The LSI53C810A uses this value for all burst data transfers.

3.2.3 Alignment

The LSI53C810A uses the calculated burst size value to monitor the current address for alignment to the cache line size. When it is not aligned, the chip disables bursting allowing only single Dword transfers until a cache line boundary is reached. When the chip is aligned, bursting is re-enabled allowing bursts in increments speciﬁed by the Cache Line Size register as explained above. If the Cache Line Size register is not set (default = 0x00), the DMODE burst size is automatically used as the cache line size.

3.2.3.1 MMOV Misalignment

The LSI53C810A does not operate in a cache alignment mode when a MMOV instruction is issued and the read and write addresses are different distances from the nearest cache line boundary. For example, if the read address is 0x21F and the write address is 0x42F, and the cache line size is eight (8), the addresses are byte aligned, but they are not the same distance from the nearest cache boundary. The read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440. In this situation, the chip does not align to cache boundaries and operates as an LSI53C810.

3-4	PCI Functional Description

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LSI 53C810A technical manual Selection of Cache Line Size, Alignment, Mmov Misalignment

Contents

Technical Manual R c h 2 0 0 Trademark Acknowledgment Audience Organization Ansi Conventions Used in This Manual PCI Special Interest GroupRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology LSI53C810A Beneﬁts Summary Scsi Performance Integration PCI PerformanceEase of Use Flexibility Reliability Testability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Chapter Functional Description Scsi Core Scripts Processor DMA Core Sdms Software The Total Scsi Solution Prefetching Scripts Instructions PCI Cache Mode Opcode Fetch Burst Capability Load and Store Instructions Loopback ModeParity Options 2 3.3 V/5 V PCI Interface Bits Used for Parity Control and Observation BIt Name Location Description Scsi Parity Errors and Interrupts Scsi Parity Control DMA Fifo Data Paths Synchronous Scsi Send Asynchronous Scsi SendAsynchronous Scsi Receive Synchronous Scsi Receive LSI53C810A Host Interface Data Paths Terminator Networks Scsi Bus InterfaceSelect/Reselect During Selection/Reselection Active or Regulated Termination Determining the Data Transfer Rate Synchronous OperationSCNTL3 Register, Bits 64 SCF20 Sxfer Register, Bits 75 TP20 SCNTL3 Register, Bits 20 CCF20Achieving Optimal Scsi Send Rates Interrupt Handling Polling and Hardware Interrupts Registers Interrupt Handling Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Istat Functional Description PCI Addressing 1 Conﬁguration Space 2.1 I/O Read Command PCI Bus Commands and Functions Supported2.2 I/O Write Command Support for PCI Cache Line Size Register Alignment Selection of Cache Line SizeMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands PCI Bus Commands and Encoding Types Conﬁguration Registers PCI Conﬁguration Register Map Register EBM EperWIE EMS DPE EISEnable I/O Space0Status Read/Write SSE RTA DPRData Parity Reported8 Register 0x09 Register 0x08RID Register 0x0D Latency Timer Read/Write LTLatency Timer70Register 0x0C Cache Line Size Read/Write Register 0x14 Register 0x0ERegister 0x10 Barz Interrupt Line Read/Write ILInterrupt Line70 Register 0x3CRegister 0x3D Interrupt Pin Read Only IPInterrupt Pin70 MinGnt Read Only MGMinGnt70 Register 0x3ERegister 0x3F MaxLat Read Only MLMaxLat70 PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Signals are assigned a type. There are four signal types Power and Ground Signals Functional Signal Grouping System Signals PCI Bus Interface SignalsSystem Signals Address and Data Signals Address and Data Signals Interface Control Signals Interface Control Signals Arbitration Signals Arbitration SignalsError Reporting Signals Error Reporting Signals Scsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface Signals MAC Signal Descriptions Chapter Operating Registers Register 0x00 Scsi Control Zero SCNTL0 Read/Write Simple Arbitration ARB10 Arbitration Mode Bits 1Full Arbitration, Selection/Reselection Start Sequence StartWatn Select with SATN/ on a Start Sequence4 AAP EPCTRG ADB Register 0x01EXC DHP Aesp CONRST Iarb SSTStart Scsi Transfer0 Register 0x03 Register 0x02SDU Reserved CCF20 Clock Conversion Factor RRE Register 0x04SRE Scsi Transfer Sxfer Read/Write Register 0x05Reserved ENC20 Encoded LSI53C810A Chip Scsi ID TP20 Scsi Synchronous Transfer Period75 TP2 TP1 TP0 Xferp Reserved MO30 Max Scsi Synchronous Offset Sclk SCNTL3 Scsi Destination ID Sdid Read/Write Register 0x06Scsi Synchronous Offset Values Reserved ENC20 Encoded destination Scsi ID General Purpose Gpreg Read/Write Register 0x07Reserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write BSY REQACK SEL VAL Register 0x0A 0x8AScsi Selector ID Ssid Read Only Scsi Valid Bit Register 0x0B 0x8B Register 0x0C 0x8C Abrt DFEMdpe SSI ILF Register 0x0D 0x8DIID ORF LOA OLFAIP WOA FF30 Fifo Flags Register 0x0E 0x8EScsi Status One SSTAT1 Read Only Sdpl Latched Scsi Parity3 Scsi Status Two SSTAT2 Read Only Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ SignalRegister 0x0F 0x8F Ldsc Registers 0x10-0x13 DSA Sigp SrstSEM Interrupt-on-the-Fly IntfSipscsi Interrupt Pending1 Chip Test Zero CTEST0 Read/Write Register 0x18Dipdma Interrupt Pending0 FMTByte Empty in DMA FIFO70 Register 0x1A 0x9A Register 0x19Ddir Dreq CIOTeop Dack FLF Register 0x1B 0x9BCLF Temp Registers 0x1C-0x1F 0x9C-0x9FRegister 0x20 0xA0 DMA Fifo Dfifo Chip Test Four CTEST4 Read/Write Burst DisableRegister 0x21 0xA1 Bdis ZSD ZmodSrtm Adck Register 0x22 0xA2Bbck Chip Test Six CTEST6 Read/Write Register 0x23 0xA3Masr Dfdma FIFO70 DBC Registers 0x24-0x26 0xA4-0xA6DMA Byte Counter DBC Read/Write DMA Byte Counter 230 Registers 0x2C-0x2F 0xAC-0xAF Register 0x27 0xA7Registers 0x28-0x2B 0xA8-0xAB Dnad Dsps Registers 0x30-0x33 0xB0-0xB3DMA Scripts Pointer Save Dsps Read/Write DMA Scripts Pointer Save 310 Register 0x38 0xB8 Registers 0x34-0x37 0xB4-0xB7Scratcha ERLEnable Read Line3 Source I/O Memory EnableDestination I/O Memory Enable Siom BOF Burst Opcode Fetch EnableErmp MANManual Start Mode0 Register 0x39 0xB9 SIR Register 0x3A 0xBA Register 0x3B 0xBB STD SSMIrqm Irqd Adder Sum Output Adder Read Only Register 0x3C-0x3F 0xBC-0xBFCOM Adder RSL Register 0x40 0xC0CMP SGE Unexpected Disconnect Scsi Reset ConditionUDC PAR GEN Register 0x41 0xC1STO HTH Scsi Interrupt Status Zero SIST0 Read Only Initiator Mode Phase Mismatch Target Mode SATN/ ActiveRegister 0x42 0xC2 CMPFunction Complete6 Transfer Sxfer register Scsi RST/ Received Parity ErrorRegister 0x43 0xC3 Scsi Interrupt Status One SIST1 Read Only Scsi Longitudinal Parity Slpar Read/Write Handshake-to-Handshake Timer ExpiredRegister 0x44 0xC4 Slpar Scsi Longitudinal Parity70 Register 0x46 0xC6 Memory Access Control Macntl Read/WriteTYP30 Chip Type DRD Register 0x47 0xC7DWR Pscpt Register 0x48 0xC8 Scsi Timer Zero STIME0 Read/WriteHTH30 Handshake-to-Handshake Timer Period GPIO0EN Register 0x49 0xC9 Scsi Timer One STIME1 Read/WriteReserved GEN30 General Purpose Timer Period SELSelection Time-Out30 Register 0x4A 0xCA Response ID Respid Read/Write Respid Response ID70 SLT Register 0x4C 0xCCSsaid ART Sclk Register 0x4D 0xCDSiso ROF Register 0x4E 0xCESCE SLB EXT Register 0x4F 0xCFLOW DSI STRHSC TTM Scsi Input Data Latch Sidl Read Only Register 0x50 0xD0Stwscsi Fifo Test Write0 Sidlscsi Input Data Latch150 Registers 0x54 0xD4 Registers 0x58 0xD8 Low Level Register Interface Mode Chapter Instruction Set Processor Scsi Scripts Sample Operation Scripts Instructions Instruction Set of the I/O Processor Block Move Instructions Scripts Overview IT10 Instruction Type Block Move 3130 Indirect Addressing First DwordDirect Addressing TIA Table Indirect Addressing Block Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Second DwordStart Address 310 I/O Instruction IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 Reselect Instruction Disconnect Instruction Wait Select Instruction Set Instruction I/O Instruction Register Clear Instruction Select Instruction Wait Disconnect Instruction Wait Reselect Instruction Relative Addressing Mode TITable Indirect Mode25 Table Indirect DirectRelative Endid Set/Clear Satn Set/Clear SackSAStart Address310 Read/Write Instructions Read-Modify-Write Cycles Move To/From Sfbr Cycles Read/Write Register Instruction Read/Write Instructions Byte Received Sfbr Transfer Control Instructions Jump Instruction Call Instruction Return Instruction Instruction Type Transfer Control Interrupt Instruction Interrupt on-the-Fly Instruction Jump/Call an Absolute Address RARelative Addressing Mode23Jump/Call a Relative Address JMP Jump If True/False WVP DCM Jump Address 310 Memory Move Instructions Memory to Memory Move Instruction TC230 Transfer Count Third DwordNo Flush Temp Register 310 Load and Store Instructions Read/Write System Memory from a Scripts Instruction DSA Relative IT20 Instruction Type 3129Reserved 2726 No Flush Store instruction only Scripts instruction prefetching, see , Func This bit has no effect unless the Prefetch Enable bitDMA Control Dcntl register is set. For information on Memory/IO Address / DSA Offset 310 Load and Store Instruction Format Chapter Electrical Characteristics DC Characteristics Absolute Maximum Stress Ratings Operating Conditions Scsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, Srst Scsi Signals-SD70/, SDP/, SREQ/, SackInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signal-IRQ Output Signals-MAC/TESTOUT, REQCapacitance 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy DEVSEL/, STOP/, PERR/, PAR 11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER 12 TolerANT Technology Electrical Characteristics Pqfp Rise and Fall Time Test Conditions Input Current as a Function of Input Voltage AC Characteristics Clock Timing Reset Input 14 Reset Input TimingInterrupt Output Target Timing PCI Interface Timing DiagramsInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Interface Timing PCI Timing Scsi Timings 17 Initiator Asynchronous Send 5 Mbytes/s 18 Initiator Asynchronous Receive 5 Mbytes/s 20 Initiator Asynchronous Receive 19 Target Asynchronous Send 5 Mbytes/s 21 Target Asynchronous Send 20 Target Asynchronous Receive 5 Mbytes/s 22 Target Asynchronous Receive 21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings 24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Symbols Numerics IX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Reader’s Comments Excellent Good Average Fair Distributors by State California New York Direct Sales Representatives by State Component and Boards Sales Ofﬁces and Design Resource Centers International International Distributors