when the LSI53C810A operates in the initiator mode. When the LSI53C810A operates in low level mode, any disconnect causes an interrupt, even a valid SCSI disconnect. This bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the STO interrupt, since this is not considered an expected disconnect).

RST

SCSI RST/ Received

1

 

This bit is set when the LSI53C810A detects an active

 

 

SRST/ signal, whether the reset was generated external

 

to the chip or caused by the Assert SRST/ bit in the SCSI

 

Control One (SCNTL1) register. This SCSI reset

 

 

detection logic is edge-sensitive, so that multiple

 

 

interrupts are not generated for a single assertion of the

 

SRST/ signal.

 

PAR

Parity Error

0

 

This bit is set when the LSI53C810A detects a parity

 

 

error while receiving SCSI data. The Enable Parity

 

 

Checking bit (bit 3 in the SCSI Control Zero (SCNTL0)

 

 

register) must be set for this bit to become active. The

 

LSI53C810A always generates parity when sending SCSI data.

Register: 0x43 (0xC3)

SCSI Interrupt Status One (SIST1)

Read Only

7

 

 

 

3

2

1

0

 

 

R

 

 

STO

GEN

HTH

x

x

x

x

x

0

0

0

 

 

 

 

 

 

 

 

Reading the SCSI Interrupt Status One (SIST1) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable One (SIEN1) register or not. Each bit that is set indicates an occurrence of the corresponding condition.

Reading the SCSI Interrupt Status One (SIST1) register clears the interrupt condition.

5-53

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Image 127
LSI 53C810A Register 0x43 0xC3, Scsi RST/ Received, Parity Error, Scsi Interrupt Status One SIST1 Read Only