LSI53C810A Pin Diagram | LSI guide

Figure 4.1 LSI53C810A Pin Diagram

AD21

AD20

VDD-I

AD19

VSS-I

AD18

AD17

AD16

VSS-I C_BE2/

FRAME/

IRDY/

VSS-I

TRDY/

DEVSEL/

VDD-I

STOP/

VSS-I

PERR/

PAR C_BE1/

VSS-I

AD15

AD14

AD13

VSS-I

AD12

VDD-I

AD11

AD10

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

AD22	V			AD23		IDSEL		BE3/C		AD24		AD25		V		AD26		AD27		V		AD28		AD29		VSS-I		AD30		AD31		V		REQ/		GNT V
	I -													I -						I -												C -						C -
		SS													SS						DD												DD						SS



100	99			98		97		96		95		94		93		92		91		90		89		88		87		86		85		84		83		82		81

LSI53C810A

100-pin Quad Flat Pack

31	32			33		34		35		36		37			38		39		40			41		42		43			44		45		46			47		48		49		50



AD9	V			AD8		C BE0/		AD7		AD6		V			AD5		AD4		V			AD3		AD2		V			AD1		AD0		V			IRQ/		GPIO0FETCH/		MASTER/GPIO1		V
	I -											I							I							I -							C									C
	I -											-							-							I -							C									C
		SS											SS							DD							SS							DD									SS
																																	-									-

80 CLK

79 RST/

78 SERR/

77 VDD-S

76 SD0/

75 SD1/

74 SD2/

73 VSS-S

72 SD3/

71 SD4/

70 SD5/

69 SD6/

68 VSS-S

67 SD7/

66 SDP/

65 SATN/

64 SBSY/

63 VSS-S

62 SACK/

61 SRST/

60 SMSG/

59 SSEL/

58 VSS-S

57 SCD/

56 SREQ/

55 SIO/

54			VDD-S
53			MAC/_TESTOUT
52			TESTIN
51			SCLK

A slash (/) at the end of the signal name indicates that the active state occurs when the signal is at a LOW voltage. When the slash is absent, the signal is active at a HIGH voltage.

4-2	Signal Descriptions

Image 64

LSI technical manual LSI53C810A Pin Diagram

Contents

Technical Manual R c h 2 0 0 Trademark Acknowledgment Audience Organization Ansi Conventions Used in This Manual PCI Special Interest GroupRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology LSI53C810A Beneﬁts Summary Scsi Performance Integration PCI PerformanceEase of Use Flexibility Reliability Testability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Chapter Functional Description Scsi Core Scripts Processor DMA Core Sdms Software The Total Scsi Solution Prefetching Scripts Instructions PCI Cache Mode Opcode Fetch Burst Capability Loopback Mode Parity OptionsLoad and Store Instructions 2 3.3 V/5 V PCI Interface Bits Used for Parity Control and Observation BIt Name Location Description Scsi Parity Errors and Interrupts Scsi Parity Control DMA Fifo Data Paths Synchronous Scsi Send Asynchronous Scsi SendAsynchronous Scsi Receive Synchronous Scsi Receive LSI53C810A Host Interface Data Paths Terminator Networks Scsi Bus InterfaceSelect/Reselect During Selection/Reselection Active or Regulated Termination Determining the Data Transfer Rate Synchronous OperationSCNTL3 Register, Bits 64 SCF20 Sxfer Register, Bits 75 TP20 SCNTL3 Register, Bits 20 CCF20Achieving Optimal Scsi Send Rates Interrupt Handling Polling and Hardware Interrupts Registers Interrupt Handling Fatal vs. Nonfatal Interrupts Masking Stacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status Istat Functional Description PCI Addressing 1 Conﬁguration Space 2.1 I/O Read Command PCI Bus Commands and Functions Supported2.2 I/O Write Command Support for PCI Cache Line Size Register Alignment Selection of Cache Line SizeMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands PCI Bus Commands and Encoding Types Conﬁguration Registers PCI Conﬁguration Register Map Register Eper WIEEBM EMS EISEnable I/O Space0 Status Read/WriteDPE SSE RTA DPRData Parity Reported8 Register 0x09 Register 0x08RID Latency Timer Read/Write LTLatency Timer70 Register 0x0CRegister 0x0D Cache Line Size Read/Write Register 0x0E Register 0x10Register 0x14 Barz Register 0x3C Register 0x3DInterrupt Line Read/Write ILInterrupt Line70 Interrupt Pin Read Only IPInterrupt Pin70 Register 0x3E Register 0x3FMinGnt Read Only MGMinGnt70 MaxLat Read Only MLMaxLat70 PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Signals are assigned a type. There are four signal types Power and Ground Signals Functional Signal Grouping System Signals PCI Bus Interface SignalsSystem Signals Address and Data Signals Address and Data Signals Interface Control Signals Interface Control Signals Arbitration Signals Error Reporting SignalsArbitration Signals Error Reporting Signals Scsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface Signals MAC Signal Descriptions Chapter Operating Registers Register 0x00 Scsi Control Zero SCNTL0 Read/Write Simple Arbitration ARB10 Arbitration Mode Bits 1Full Arbitration, Selection/Reselection Start Sequence StartWatn Select with SATN/ on a Start Sequence4 AAP EPCTRG Register 0x01 EXCADB DHP CON RSTAesp Iarb SSTStart Scsi Transfer0 Register 0x03 Register 0x02SDU Reserved CCF20 Clock Conversion Factor RRE Register 0x04SRE Register 0x05 Reserved ENC20 Encoded LSI53C810A Chip Scsi IDScsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer Period75 TP2 TP1 TP0 Xferp Reserved MO30 Max Scsi Synchronous Offset Sclk SCNTL3 Register 0x06 Scsi Synchronous Offset ValuesScsi Destination ID Sdid Read/Write Reserved ENC20 Encoded destination Scsi ID General Purpose Gpreg Read/Write Register 0x07Reserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write REQ ACKBSY SEL Register 0x0A 0x8A Scsi Selector ID Ssid Read OnlyVAL Scsi Valid Bit Register 0x0B 0x8B Register 0x0C 0x8C DFE MdpeAbrt SSI Register 0x0D 0x8D IIDILF ORF OLF AIPLOA WOA Register 0x0E 0x8E Scsi Status One SSTAT1 Read OnlyFF30 Fifo Flags Sdpl Latched Scsi Parity3 Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ Signal Register 0x0F 0x8FScsi Status Two SSTAT2 Read Only Ldsc Registers 0x10-0x13 DSA Sigp SrstSEM Interrupt-on-the-Fly IntfSipscsi Interrupt Pending1 Register 0x18 Dipdma Interrupt Pending0Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70 Register 0x1A 0x9A Register 0x19Ddir CIO TeopDreq Dack FLF Register 0x1B 0x9BCLF Registers 0x1C-0x1F 0x9C-0x9F Register 0x20 0xA0Temp DMA Fifo Dfifo Burst Disable Register 0x21 0xA1Chip Test Four CTEST4 Read/Write Bdis ZSD ZmodSrtm Adck Register 0x22 0xA2Bbck Register 0x23 0xA3 MasrChip Test Six CTEST6 Read/Write Dfdma FIFO70 Registers 0x24-0x26 0xA4-0xA6 DMA Byte Counter DBC Read/WriteDBC DMA Byte Counter 230 Register 0x27 0xA7 Registers 0x28-0x2B 0xA8-0xABRegisters 0x2C-0x2F 0xAC-0xAF Dnad Registers 0x30-0x33 0xB0-0xB3 DMA Scripts Pointer Save Dsps Read/WriteDsps DMA Scripts Pointer Save 310 Register 0x38 0xB8 Registers 0x34-0x37 0xB4-0xB7Scratcha Source I/O Memory Enable Destination I/O Memory EnableERLEnable Read Line3 Siom Burst Opcode Fetch Enable ErmpBOF MANManual Start Mode0 Register 0x39 0xB9 SIR Register 0x3A 0xBA Register 0x3B 0xBB SSM IrqmSTD Irqd Register 0x3C-0x3F 0xBC-0xBF COMAdder Sum Output Adder Read Only Adder Register 0x40 0xC0 CMPRSL SGE Scsi Reset Condition UDCUnexpected Disconnect PAR Register 0x41 0xC1 STOGEN HTH Initiator Mode Phase Mismatch Target Mode SATN/ Active Register 0x42 0xC2Scsi Interrupt Status Zero SIST0 Read Only CMPFunction Complete6 Transfer Sxfer register Parity Error Register 0x43 0xC3Scsi RST/ Received Scsi Interrupt Status One SIST1 Read Only Handshake-to-Handshake Timer Expired Register 0x44 0xC4Scsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70 Register 0x46 0xC6 Memory Access Control Macntl Read/WriteTYP30 Chip Type Register 0x47 0xC7 DWRDRD Pscpt Scsi Timer Zero STIME0 Read/Write HTH30 Handshake-to-Handshake Timer PeriodRegister 0x48 0xC8 GPIO0EN Scsi Timer One STIME1 Read/Write Reserved GEN30 General Purpose Timer PeriodRegister 0x49 0xC9 SELSelection Time-Out30 Register 0x4A 0xCA Response ID Respid Read/Write Respid Response ID70 Register 0x4C 0xCC SsaidSLT ART Sclk Register 0x4D 0xCDSiso Register 0x4E 0xCE SCEROF SLB EXT Register 0x4F 0xCFLOW STR HSCDSI TTM Register 0x50 0xD0 Stwscsi Fifo Test Write0Scsi Input Data Latch Sidl Read Only Sidlscsi Input Data Latch150 Registers 0x54 0xD4 Registers 0x58 0xD8 Low Level Register Interface Mode Chapter Instruction Set Processor Scsi Scripts Sample Operation Scripts Instructions Instruction Set of the I/O Processor Block Move Instructions Scripts Overview IT10 Instruction Type Block Move 3130 Indirect Addressing First DwordDirect Addressing TIA Table Indirect Addressing Block Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Second DwordStart Address 310 I/O Instruction IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 Reselect Instruction Disconnect Instruction Wait Select Instruction Set Instruction I/O Instruction Register Clear Instruction Select Instruction Wait Disconnect Instruction Wait Reselect Instruction Relative Addressing Mode TITable Indirect Mode25 Table Indirect DirectRelative Endid Set/Clear Satn Set/Clear SackSAStart Address310 Read/Write Instructions Read-Modify-Write Cycles Move To/From Sfbr Cycles Read/Write Register Instruction Read/Write Instructions Byte Received Sfbr Transfer Control Instructions Jump Instruction Call Instruction Return Instruction Instruction Type Transfer Control Interrupt Instruction Interrupt on-the-Fly Instruction Jump/Call an Absolute Address RARelative Addressing Mode23Jump/Call a Relative Address JMP Jump If True/False WVP DCM Jump Address 310 Memory Move Instructions Memory to Memory Move Instruction Third Dword No FlushTC230 Transfer Count Temp Register 310 Load and Store Instructions Read/Write System Memory from a Scripts Instruction DSA Relative IT20 Instruction Type 3129Reserved 2726 No Flush Store instruction only This bit has no effect unless the Prefetch Enable bit DMA Control Dcntl register is set. For information onScripts instruction prefetching, see , Func Memory/IO Address / DSA Offset 310 Load and Store Instruction Format Chapter Electrical Characteristics DC Characteristics Absolute Maximum Stress Ratings Operating Conditions Scsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, Srst Scsi Signals-SD70/, SDP/, SREQ/, SackInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signal-IRQ Output Signals-MAC/TESTOUT, REQCapacitance 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy DEVSEL/, STOP/, PERR/, PAR 11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER 12 TolerANT Technology Electrical Characteristics Pqfp Rise and Fall Time Test Conditions Input Current as a Function of Input Voltage AC Characteristics Clock Timing Reset Input 14 Reset Input TimingInterrupt Output Target Timing PCI Interface Timing DiagramsInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Interface Timing PCI Timing Scsi Timings 17 Initiator Asynchronous Send 5 Mbytes/s 18 Initiator Asynchronous Receive 5 Mbytes/s 20 Initiator Asynchronous Receive 19 Target Asynchronous Send 5 Mbytes/s 21 Target Asynchronous Send 20 Target Asynchronous Receive 5 Mbytes/s 22 Target Asynchronous Receive 21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings 24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Symbols Numerics IX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Reader’s Comments Excellent Good Average Fair Distributors by State California New York Direct Sales Representatives by State Component and Boards Sales Ofﬁces and Design Resource Centers International International Distributors