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LSI 53C810A Register 0x42 0xC2, Scsi Interrupt Status Zero SIST0 Read Only, CMPFunction Complete6

Models: 53C810A

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Register: 0x42 (0xC2)

SCSI Interrupt Status Zero (SIST0)

Read Only

7	6	5	4	3	2	1	0
M/A	CMP	SEL	RSL	SGE	UDC	RST	PAR

0	0	0	0	0	0	0	0

Reading the SCSI Interrupt Status Zero (SIST0) register returns the status of the various interrupt conditions, whether they are enabled in the SCSI Interrupt Enable Zero (SIEN0) register or not. Each bit set indicates an occurrence of the corresponding condition. Reading the SCSI Interrupt Status Zero (SIST0) clears the interrupt status.

Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C810A stacks interrupts). SCSI interrupt conditions may be individually masked through the SCSI Interrupt Enable Zero (SIEN0) register.

When performing consecutive 8-bit reads of the DMA Status (DSTAT), SCSI Interrupt Status Zero (SIST0), and SCSI Interrupt Status One (SIST1) registers (in any order), insert a delay equivalent to 12 CLK periods between the reads to ensure the interrupts clear properly. Also, if reading the registers when both the Interrupt Status (ISTAT) SIP and DIP bits may not be set, read the SCSI Interrupt Status Zero (SIST0) and SCSI Interrupt Status One (SIST1) registers the DMA Status (DSTAT) register to avoid missing a SCSI interrupt. For more information on interrupts, refer to Chapter 2, “Functional Description.”

M/A	Initiator Mode: Phase Mismatch;
	Target Mode: SATN/ Active	7
	In the initiator mode, this bit is set if the SCSI phase
	asserted by the target does not match the instruction.
	The phase is sampled when SREQ/ is asserted by the
	target. In target mode, this bit is set when the SATN/
	signal is asserted by the initiator.

CMPFunction Complete6

This bit is set when an arbitration only or full arbitration sequence is completed.

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LSI 53C810A technical manual Register 0x42 0xC2, Scsi Interrupt Status Zero SIST0 Read Only, CMPFunction Complete6

Contents

R c h 2 0 0 Technical ManualTrademark Acknowledgment Organization AudienceAnsi Revision Record PCI Special Interest GroupConventions Used in This Manual ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology Scsi Performance LSI53C810A Beneﬁts SummaryEase of Use PCI PerformanceIntegration Reliability FlexibilityTestability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Scsi Core Chapter Functional DescriptionDMA Core Scripts ProcessorPrefetching Scripts Instructions Sdms Software The Total Scsi SolutionOpcode Fetch Burst Capability PCI Cache ModeParity Options Loopback ModeLoad and Store Instructions 2 3.3 V/5 V PCI InterfaceBIt Name Location Description Bits Used for Parity Control and ObservationScsi Parity Control Scsi Parity Errors and InterruptsData Paths DMA FifoAsynchronous Scsi Receive Asynchronous Scsi SendSynchronous Scsi Send LSI53C810A Host Interface Data Paths Synchronous Scsi ReceiveSelect/Reselect During Selection/Reselection Scsi Bus InterfaceTerminator Networks Active or Regulated Termination SCNTL3 Register, Bits 64 SCF20 Synchronous OperationDetermining the Data Transfer Rate Achieving Optimal Scsi Send Rates SCNTL3 Register, Bits 20 CCF20Sxfer Register, Bits 75 TP20 Polling and Hardware Interrupts Interrupt HandlingRegisters Interrupt Handling Masking Fatal vs. Nonfatal InterruptsStacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Istat Sample Interrupt Service RoutineFunctional Description 1 Conﬁguration Space PCI Addressing2.2 I/O Write Command PCI Bus Commands and Functions Supported2.1 I/O Read Command Support for PCI Cache Line Size Register Mmov Misalignment Selection of Cache Line SizeAlignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands Conﬁguration Registers PCI Bus Commands and Encoding TypesPCI Conﬁguration Register Map Register WIE EperEBM EMSStatus Read/Write EISEnable I/O Space0DPE SSEDPRData Parity Reported8 RTARID Register 0x08Register 0x09 Register 0x0C Latency Timer Read/Write LTLatency Timer70Register 0x0D Cache Line Size Read/WriteRegister 0x10 Register 0x0ERegister 0x14 BarzRegister 0x3D Register 0x3CInterrupt Line Read/Write ILInterrupt Line70 Interrupt Pin Read Only IPInterrupt Pin70Register 0x3F Register 0x3EMinGnt Read Only MGMinGnt70 MaxLat Read Only MLMaxLat70PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Power and Ground Signals Signals are assigned a type. There are four signal typesFunctional Signal Grouping System Signals PCI Bus Interface SignalsSystem Signals Address and Data Signals Address and Data SignalsInterface Control Signals Interface Control SignalsError Reporting Signals Arbitration SignalsArbitration Signals Error Reporting SignalsScsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface SignalsMAC Signal Descriptions Chapter Operating Registers Scsi Control Zero SCNTL0 Read/Write Register 0x00Full Arbitration, Selection/Reselection ARB10 Arbitration Mode Bits 1Simple Arbitration Watn Select with SATN/ on a Start Sequence4 StartStart Sequence TRG EPCAAP EXC Register 0x01ADB DHPRST CONAesp IarbSSTStart Scsi Transfer0 SDU Register 0x02Register 0x03 Reserved CCF20 Clock Conversion Factor SRE Register 0x04RRE Reserved ENC20 Encoded LSI53C810A Chip Scsi ID Register 0x05Scsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer Period75TP2 TP1 TP0 Xferp Sclk SCNTL3 Reserved MO30 Max Scsi Synchronous OffsetScsi Synchronous Offset Values Register 0x06Scsi Destination ID Sdid Read/Write Reserved ENC20 Encoded destination Scsi IDReserved GPIO10 General Purpose Register 0x07General Purpose Gpreg Read/Write Scsi First Byte Received Sfbr Read/Write ACK REQBSY SELScsi Selector ID Ssid Read Only Register 0x0A 0x8AVAL Scsi Valid BitRegister 0x0C 0x8C Register 0x0B 0x8BMdpe DFEAbrt SSIIID Register 0x0D 0x8DILF ORFAIP OLFLOA WOAScsi Status One SSTAT1 Read Only Register 0x0E 0x8EFF30 Fifo Flags Sdpl Latched Scsi Parity3Register 0x0F 0x8F Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ SignalScsi Status Two SSTAT2 Read Only LdscDSA Registers 0x10-0x13SEM SrstSigp Sipscsi Interrupt Pending1 IntfInterrupt-on-the-Fly Dipdma Interrupt Pending0 Register 0x18Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70Ddir Register 0x19Register 0x1A 0x9A Teop CIODreq DackCLF Register 0x1B 0x9BFLF Register 0x20 0xA0 Registers 0x1C-0x1F 0x9C-0x9FTemp DMA Fifo DfifoRegister 0x21 0xA1 Burst DisableChip Test Four CTEST4 Read/Write BdisSrtm ZmodZSD Bbck Register 0x22 0xA2Adck Masr Register 0x23 0xA3Chip Test Six CTEST6 Read/Write Dfdma FIFO70DMA Byte Counter DBC Read/Write Registers 0x24-0x26 0xA4-0xA6DBC DMA Byte Counter 230Registers 0x28-0x2B 0xA8-0xAB Register 0x27 0xA7Registers 0x2C-0x2F 0xAC-0xAF DnadDMA Scripts Pointer Save Dsps Read/Write Registers 0x30-0x33 0xB0-0xB3Dsps DMA Scripts Pointer Save 310Scratcha Registers 0x34-0x37 0xB4-0xB7Register 0x38 0xB8 Destination I/O Memory Enable Source I/O Memory EnableERLEnable Read Line3 SiomErmp Burst Opcode Fetch EnableBOF MANManual Start Mode0SIR Register 0x39 0xB9Register 0x3B 0xBB Register 0x3A 0xBAIrqm SSMSTD IrqdCOM Register 0x3C-0x3F 0xBC-0xBFAdder Sum Output Adder Read Only AdderCMP Register 0x40 0xC0RSL SGEUDC Scsi Reset ConditionUnexpected Disconnect PARSTO Register 0x41 0xC1GEN HTHRegister 0x42 0xC2 Initiator Mode Phase Mismatch Target Mode SATN/ ActiveScsi Interrupt Status Zero SIST0 Read Only CMPFunction Complete6Transfer Sxfer register Register 0x43 0xC3 Parity ErrorScsi RST/ Received Scsi Interrupt Status One SIST1 Read OnlyRegister 0x44 0xC4 Handshake-to-Handshake Timer ExpiredScsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70TYP30 Chip Type Memory Access Control Macntl Read/WriteRegister 0x46 0xC6 DWR Register 0x47 0xC7DRD PscptHTH30 Handshake-to-Handshake Timer Period Scsi Timer Zero STIME0 Read/WriteRegister 0x48 0xC8 GPIO0ENReserved GEN30 General Purpose Timer Period Scsi Timer One STIME1 Read/WriteRegister 0x49 0xC9 SELSelection Time-Out30Response ID Respid Read/Write Respid Response ID70 Register 0x4A 0xCASsaid Register 0x4C 0xCCSLT ARTSiso Register 0x4D 0xCDSclk SCE Register 0x4E 0xCEROF SLBLOW Register 0x4F 0xCFEXT HSC STRDSI TTMStwscsi Fifo Test Write0 Register 0x50 0xD0Scsi Input Data Latch Sidl Read Only Sidlscsi Input Data Latch150Registers 0x58 0xD8 Registers 0x54 0xD4Chapter Instruction Set Processor Low Level Register Interface ModeScsi Scripts Scripts Instructions Sample OperationInstruction Set of the I/O Processor Scripts Overview Block Move InstructionsDirect Addressing First DwordIT10 Instruction Type Block Move 3130 Indirect Addressing Table Indirect Addressing TIABlock Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 Start Address 310 Second DwordTC230 Transfer Counter230 IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 I/O InstructionDisconnect Instruction Reselect InstructionSet Instruction Wait Select InstructionI/O Instruction Register Select Instruction Clear InstructionWait Reselect Instruction Wait Disconnect InstructionTITable Indirect Mode25 Relative Addressing ModeRelative DirectTable Indirect Endid SAStart Address310 Set/Clear SackSet/Clear Satn Read-Modify-Write Cycles Read/Write InstructionsMove To/From Sfbr Cycles Read/Write Register Instruction Byte Received Sfbr Read/Write InstructionsTransfer Control Instructions Call Instruction Jump InstructionReturn Instruction Instruction Type Transfer Control Interrupt on-the-Fly Instruction Interrupt InstructionJump/Call a Relative Address RARelative Addressing Mode23Jump/Call an Absolute Address Jump If True/False JMPDCM WVPJump Address 310 Memory Move Instructions Memory to Memory Move Instruction No Flush Third DwordTC230 Transfer Count Temp Register 310Read/Write System Memory from a Scripts Instruction Load and Store InstructionsReserved 2726 No Flush Store instruction only IT20 Instruction Type 3129DSA Relative DMA Control Dcntl register is set. For information on This bit has no effect unless the Prefetch Enable bitScripts instruction prefetching, see , Func Memory/IO Address / DSA Offset 310Load and Store Instruction Format DC Characteristics Chapter Electrical CharacteristicsOperating Conditions Absolute Maximum Stress RatingsInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Scsi Signals-SD70/, SDP/, SREQ/, SackScsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, Srst Capacitance Output Signals-MAC/TESTOUT, REQOutput Signal-IRQ DEVSEL/, STOP/, PERR/, PAR 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER Pqfp 12 TolerANT Technology Electrical CharacteristicsRise and Fall Time Test Conditions Input Current as a Function of Input Voltage Clock Timing AC CharacteristicsInterrupt Output 14 Reset Input TimingReset Input Initiator Timing PCI Interface Timing DiagramsTarget Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Timing PCI Interface Timing17 Initiator Asynchronous Send 5 Mbytes/s Scsi Timings20 Initiator Asynchronous Receive 18 Initiator Asynchronous Receive 5 Mbytes/s21 Target Asynchronous Send 19 Target Asynchronous Send 5 Mbytes/s22 Target Asynchronous Receive 20 Target Asynchronous Receive 5 Mbytes/s21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Numerics SymbolsIX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Excellent Good Average Fair Reader’s CommentsCalifornia Distributors by StateNew York Direct Sales Representatives by State Component and Boards International Sales Ofﬁces and Design Resource CentersInternational Distributors