operating register set of the chip. If it does, a PCI illegal read/write cycle occur, the chip issues an interrupt (Illegal Instruction Detected) immediately following.

Bits A1, A0

Number of Bytes Allowed to Load/Store

00One, two, three or four

01One, two, or three

10One or two

11One

The SIOM and DIOM bits in the DMA Mode (DMODE) register determine whether the destination or source address of the instruction is in Memory space or I/O space. The Load and Store utilizes the PCI commands for I/O read and I/O write to access the I/O space.

6.8.1 First Dword

IT[2:0]

Instruction Type

[31:29]

 

These bits should be 111, indicating the Load and Store

 

instruction.

 

DSA

DSA Relative

28

 

When this bit is cleared, the value in the DMA SCRIPTS

 

Pointer Save (DSPS) is the actual 32-bit memory address

 

used to perform the Load and Store to/from. When this

 

bit is set, the chip determines the memory address to

 

perform the Load and Store to/from by adding the 24-bit

 

signed offset value in the DMA SCRIPTS Pointer Save

 

(DSPS) to the Data Structure Address (DSA).

 

R

Reserved

[27:26]

NF

No Flush (Store instruction only)

25

 

When this bit is set, the LSI53C810A performs a Store

 

without flushing the prefetch unit. When this bit is cleared,

 

the Store instruction automatically flushes the prefetch

 

unit. Use No Flush if the source and destination are not

 

within four instructions of the current Store instruction.

6-40

Instruction Set of the I/O Processor

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LSI 53C810A technical manual IT20 Instruction Type 3129, DSA Relative, Reserved 2726 No Flush Store instruction only