Chapter Operating Registers | LSI 53C810A manual

Chapter 5

Operating Registers

This chapter describes all LSI53C810A operating registers. Table 5.1, the register map, lists registers by operating and conﬁguration addresses. The terms “set” and “assert” are used to refer to bits that are programmed to a binary one. Similarly, the terms “deassert,” “clear,” and “reset” are used to refer to bits that are programmed to a binary zero. Any bits marked as reserved should always be written to zero; mask all information read from them. Reserved bit functions may be changed at any time. Unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. The bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset.

Note: The only register that the host CPU can access while the LSI53C810A is executing SCRIPTS is the Interrupt Status (ISTAT) register. Attempts to access other registers interferes with the operation of the chip. However, all operating registers are accessible with SCRIPTS. All read data is synchronized and stable when presented to the PCI bus.

The LSI53C810A cannot fetch SCRIPTS instructions from the operating register space. Fetch instructions from system memory.

LSI53C810A PCI to SCSI I/O Processor

5-1

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LSI 53C810A technical manual Chapter Operating Registers

Contents

R c h 2 0 0 Technical Manual Trademark Acknowledgment Organization Audience Ansi PCI Special Interest Group Conventions Used in This ManualRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology Scsi Performance LSI53C810A Beneﬁts Summary PCI Performance IntegrationEase of Use Reliability Flexibility Testability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Scsi Core Chapter Functional Description DMA Core Scripts Processor Prefetching Scripts Instructions Sdms Software The Total Scsi Solution Opcode Fetch Burst Capability PCI Cache Mode 2 3.3 V/5 V PCI Interface Loopback ModeParity Options Load and Store Instructions BIt Name Location Description Bits Used for Parity Control and Observation Scsi Parity Control Scsi Parity Errors and Interrupts Data Paths DMA Fifo Asynchronous Scsi Send Synchronous Scsi SendAsynchronous Scsi Receive LSI53C810A Host Interface Data Paths Synchronous Scsi Receive Scsi Bus Interface Terminator NetworksSelect/Reselect During Selection/Reselection Active or Regulated Termination Synchronous Operation Determining the Data Transfer RateSCNTL3 Register, Bits 64 SCF20 SCNTL3 Register, Bits 20 CCF20 Sxfer Register, Bits 75 TP20Achieving Optimal Scsi Send Rates Polling and Hardware Interrupts Interrupt Handling Registers Interrupt Handling Masking Fatal vs. Nonfatal Interrupts Stacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Istat Sample Interrupt Service Routine Functional Description 1 Conﬁguration Space PCI Addressing PCI Bus Commands and Functions Supported 2.1 I/O Read Command2.2 I/O Write Command Support for PCI Cache Line Size Register Selection of Cache Line Size AlignmentMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands Conﬁguration Registers PCI Bus Commands and Encoding Types PCI Conﬁguration Register Map Register EMS EperWIE EBM SSE EISEnable I/O Space0Status Read/Write DPE DPRData Parity Reported8 RTA Register 0x08 Register 0x09RID Cache Line Size Read/Write Latency Timer Read/Write LTLatency Timer70Register 0x0C Register 0x0D Barz Register 0x0ERegister 0x10 Register 0x14 Interrupt Pin Read Only IPInterrupt Pin70 Register 0x3CRegister 0x3D Interrupt Line Read/Write ILInterrupt Line70 MaxLat Read Only MLMaxLat70 Register 0x3ERegister 0x3F MinGnt Read Only MGMinGnt70 PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Power and Ground Signals Signals are assigned a type. There are four signal types Functional Signal Grouping PCI Bus Interface Signals System SignalsSystem Signals Address and Data Signals Address and Data Signals Interface Control Signals Interface Control Signals Error Reporting Signals Arbitration SignalsError Reporting Signals Arbitration Signals Scsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface Signals MAC Signal Descriptions Chapter Operating Registers Scsi Control Zero SCNTL0 Read/Write Register 0x00 ARB10 Arbitration Mode Bits 1 Simple ArbitrationFull Arbitration, Selection/Reselection Start Start SequenceWatn Select with SATN/ on a Start Sequence4 EPC AAPTRG DHP Register 0x01EXC ADB Iarb CONRST Aesp SSTStart Scsi Transfer0 Register 0x02 Register 0x03SDU Reserved CCF20 Clock Conversion Factor Register 0x04 RRESRE TP20 Scsi Synchronous Transfer Period75 Register 0x05Reserved ENC20 Encoded LSI53C810A Chip Scsi ID Scsi Transfer Sxfer Read/Write TP2 TP1 TP0 Xferp Sclk SCNTL3 Reserved MO30 Max Scsi Synchronous Offset Reserved ENC20 Encoded destination Scsi ID Register 0x06Scsi Synchronous Offset Values Scsi Destination ID Sdid Read/Write Register 0x07 General Purpose Gpreg Read/WriteReserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write SEL REQACK BSY Scsi Valid Bit Register 0x0A 0x8AScsi Selector ID Ssid Read Only VAL Register 0x0C 0x8C Register 0x0B 0x8B SSI DFEMdpe Abrt ORF Register 0x0D 0x8DIID ILF WOA OLFAIP LOA Sdpl Latched Scsi Parity3 Register 0x0E 0x8EScsi Status One SSTAT1 Read Only FF30 Fifo Flags Ldsc Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ SignalRegister 0x0F 0x8F Scsi Status Two SSTAT2 Read Only DSA Registers 0x10-0x13 Srst SigpSEM Intf Interrupt-on-the-FlySipscsi Interrupt Pending1 FMTByte Empty in DMA FIFO70 Register 0x18Dipdma Interrupt Pending0 Chip Test Zero CTEST0 Read/Write Register 0x19 Register 0x1A 0x9ADdir Dack CIOTeop Dreq Register 0x1B 0x9B FLFCLF DMA Fifo Dfifo Registers 0x1C-0x1F 0x9C-0x9FRegister 0x20 0xA0 Temp Bdis Burst DisableRegister 0x21 0xA1 Chip Test Four CTEST4 Read/Write Zmod ZSDSrtm Register 0x22 0xA2 AdckBbck Dfdma FIFO70 Register 0x23 0xA3Masr Chip Test Six CTEST6 Read/Write DMA Byte Counter 230 Registers 0x24-0x26 0xA4-0xA6DMA Byte Counter DBC Read/Write DBC Dnad Register 0x27 0xA7Registers 0x28-0x2B 0xA8-0xAB Registers 0x2C-0x2F 0xAC-0xAF DMA Scripts Pointer Save 310 Registers 0x30-0x33 0xB0-0xB3DMA Scripts Pointer Save Dsps Read/Write Dsps Registers 0x34-0x37 0xB4-0xB7 Register 0x38 0xB8Scratcha Siom Source I/O Memory EnableDestination I/O Memory Enable ERLEnable Read Line3 MANManual Start Mode0 Burst Opcode Fetch EnableErmp BOF SIR Register 0x39 0xB9 Register 0x3B 0xBB Register 0x3A 0xBA Irqd SSMIrqm STD Adder Register 0x3C-0x3F 0xBC-0xBFCOM Adder Sum Output Adder Read Only SGE Register 0x40 0xC0CMP RSL PAR Scsi Reset ConditionUDC Unexpected Disconnect HTH Register 0x41 0xC1STO GEN CMPFunction Complete6 Initiator Mode Phase Mismatch Target Mode SATN/ ActiveRegister 0x42 0xC2 Scsi Interrupt Status Zero SIST0 Read Only Transfer Sxfer register Scsi Interrupt Status One SIST1 Read Only Parity ErrorRegister 0x43 0xC3 Scsi RST/ Received Slpar Scsi Longitudinal Parity70 Handshake-to-Handshake Timer ExpiredRegister 0x44 0xC4 Scsi Longitudinal Parity Slpar Read/Write Memory Access Control Macntl Read/Write Register 0x46 0xC6TYP30 Chip Type Pscpt Register 0x47 0xC7DWR DRD GPIO0EN Scsi Timer Zero STIME0 Read/WriteHTH30 Handshake-to-Handshake Timer Period Register 0x48 0xC8 SELSelection Time-Out30 Scsi Timer One STIME1 Read/WriteReserved GEN30 General Purpose Timer Period Register 0x49 0xC9 Response ID Respid Read/Write Respid Response ID70 Register 0x4A 0xCA ART Register 0x4C 0xCCSsaid SLT Register 0x4D 0xCD SclkSiso SLB Register 0x4E 0xCESCE ROF Register 0x4F 0xCF EXTLOW TTM STRHSC DSI Sidlscsi Input Data Latch150 Register 0x50 0xD0Stwscsi Fifo Test Write0 Scsi Input Data Latch Sidl Read Only Registers 0x58 0xD8 Registers 0x54 0xD4 Chapter Instruction Set Processor Low Level Register Interface Mode Scsi Scripts Scripts Instructions Sample Operation Instruction Set of the I/O Processor Scripts Overview Block Move Instructions First Dword IT10 Instruction Type Block Move 3130 Indirect AddressingDirect Addressing Table Indirect Addressing TIA Block Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 Second Dword TC230 Transfer Counter230Start Address 310 IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 I/O Instruction Disconnect Instruction Reselect Instruction Set Instruction Wait Select Instruction I/O Instruction Register Select Instruction Clear Instruction Wait Reselect Instruction Wait Disconnect Instruction TITable Indirect Mode25 Relative Addressing Mode Direct Table IndirectRelative Endid Set/Clear Sack Set/Clear SatnSAStart Address310 Read-Modify-Write Cycles Read/Write Instructions Move To/From Sfbr Cycles Read/Write Register Instruction Byte Received Sfbr Read/Write Instructions Transfer Control Instructions Call Instruction Jump Instruction Return Instruction Instruction Type Transfer Control Interrupt on-the-Fly Instruction Interrupt Instruction RARelative Addressing Mode23 Jump/Call an Absolute AddressJump/Call a Relative Address Jump If True/False JMP DCM WVP Jump Address 310 Memory Move Instructions Memory to Memory Move Instruction Temp Register 310 Third DwordNo Flush TC230 Transfer Count Read/Write System Memory from a Scripts Instruction Load and Store Instructions IT20 Instruction Type 3129 DSA RelativeReserved 2726 No Flush Store instruction only Memory/IO Address / DSA Offset 310 This bit has no effect unless the Prefetch Enable bitDMA Control Dcntl register is set. For information on Scripts instruction prefetching, see , Func Load and Store Instruction Format DC Characteristics Chapter Electrical Characteristics Operating Conditions Absolute Maximum Stress Ratings Scsi Signals-SD70/, SDP/, SREQ/, Sack Scsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, SrstInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signals-MAC/TESTOUT, REQ Output Signal-IRQCapacitance DEVSEL/, STOP/, PERR/, PAR 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy 11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER Pqfp 12 TolerANT Technology Electrical Characteristics Rise and Fall Time Test Conditions Input Current as a Function of Input Voltage Clock Timing AC Characteristics 14 Reset Input Timing Reset InputInterrupt Output PCI Interface Timing Diagrams Target TimingInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Timing PCI Interface Timing 17 Initiator Asynchronous Send 5 Mbytes/s Scsi Timings 20 Initiator Asynchronous Receive 18 Initiator Asynchronous Receive 5 Mbytes/s 21 Target Asynchronous Send 19 Target Asynchronous Send 5 Mbytes/s 22 Target Asynchronous Receive 20 Target Asynchronous Receive 5 Mbytes/s 21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings 24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Numerics Symbols IX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Excellent Good Average Fair Reader’s Comments California Distributors by State New York Direct Sales Representatives by State Component and Boards International Sales Ofﬁces and Design Resource Centers International Distributors