5-49
•Data underflow – reading the SCSI FIFO when no
data was present.
•Data overflow – writing to the SCSI FIFO while it is
full.
•Offset underflow – receiving a SACK/ pulse in target
mode before the corresponding SREQ/ is sent.
•Offset overflow – receiving an SREQ/ pulse in the
initiator mode, and exceeding the maximum offset
(defined by the MO[3:0] bits in the SCSI Transfer
(SXFER) register).
•A phase change in the initiator mode, with an
outstanding SREQ/SACK offset.
•Residual data in SCSI FIFO – starting a transfer other
than synchronous data receive with data left in the
SCSI synchronous receive FIFO.
UDC Unexpected Disconnect 2
This bit controls whether an interrupt occurs in the case
of an unexpected disconnect. This condition only occurs
in initiator mode. It happens when the target to which the
LSI53C810A is connected disconnects from the SCSI
bus unexpectedly.See the SCSI Disconnect Unexpected
bit in the SCSI Control Two(SCNTL2) register for more
information on expected versusunexpected disconnects.
Any disconnect in low level mode causes this condition.
RST SCSI Reset Condition 1
This bit controls whether an interrupt occurs when the
SRST/ signal is asserted by the LSI53C810A or any
other SCSI device. Note that this condition is
edge-triggered, so that multiple interrupts cannot occur
because of a single SRST/ pulse.
PAR SCSI Parity Error 0
This bit controls whether an interrupt occurs when the
LSI53C810A detects a parity error while receiving or
sending SCSI data. See the Disable Halt on Parity Error
or SATN/Condition bits in the SCSI Control One
(SCNTL1) register for more information on when this
condition is actually raised.