Register: 0x40 (0xC0)

SCSI Interrupt Enable Zero (SIEN0)

Read/Write

7

6

5

4

3

2

1

0

M/A

CMP

SEL

RSL

SGE

UDC

RST

PAR

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

This register contains the interrupt mask bits that correspond to the interrupting conditions described in the SCSI Interrupt Status Zero (SIST0) register. An interrupt is masked by clearing the appropriate mask bit. For more information on interrupts, see Chapter 2, “Functional Description.”

M/A

SCSI Phase Mismatch - Initiator Mode;

 

 

SCSI ATN Condition - Target Mode

7

 

In the initiator mode, this bit is set when the SCSI phase

 

asserted by the target and sampled during SREQ/ does

 

not match the expected phase in the SCSI Output Control

 

Latch (SOCL) register. This expected phase is

 

 

automatically written by SCSI SCRIPTS. In target mode,

 

this bit is set when the initiator asserts SATN/. See the

 

 

Disable Halt on Parity Error or SATN/ Condition bit in the

 

SCSI Control One (SCNTL1) register for more

 

 

information on when this status is actually raised.

 

CMP

Function Complete

6

 

Indicates full arbitration and selection sequence is

 

 

completed.

 

SEL

Selected

5

 

Indicates the LSI53C810A is selected by a SCSI target

 

 

device. Set the Enable Response to Selection bit in the

 

SCSI Chip ID (SCID) register for this to occur.

 

RSL

Reselected

4

 

Indicates the LSI53C810A is reselected by a SCSI

 

 

initiator device. Set the Enable Response to Reselection

 

bit in the SCSI Chip ID (SCID) register for this to occur.

SGE

SCSI Gross Error

3

 

This bit controls whether an interrupt occurs when the

 

 

LSI53C810A detects a SCSI Gross Error. The following

 

conditions are considered SCSI Gross Errors:

 

5-48

Operating Registers

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LSI 53C810A technical manual Register 0x40 0xC0, Cmp, Rsl, Sge