Table 7.20 Target Asynchronous Receive (5 Mbytes/s)

Symbol

Parameter

Min

Max

Unit

 

 

 

 

 

t1

SREQ/ deasserted from SACK/ asserted

10

ns

 

 

 

 

 

t2

SREQ/ asserted from SACK/ deasserted

10

ns

 

 

 

 

 

t3

Data setup to SREQ/ asserted

0

ns

 

 

 

 

 

t4

Data hold from SACK/ asserted

0

ns

 

 

 

 

 

Figure 7.22 Target Asynchronous Receive

SREQ/

SACK/

SD[7:0],

SDP/

n

t1

n

t3

Valid n

t4

n + 1

t2

n + 1

Valid n + 1

Figure 7.23 Initiator and Target Synchronous Transfers

SREQ/ or SACK/

t3

Send Data SD[7:0], SDP/

t5

Receive Data

SD[15:0]/,

SDP[1:0]/

t1

n

t4

Valid n

t6

Valid n

t2

n + 1

Valid n + 1

Valid n + 1

7-30

Electrical Characteristics

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LSI 53C810A technical manual Target Asynchronous Receive 5 Mbytes/s