7.5 PCI Interface Timing

 

Table 7.16 describes the PCI timing data for the LSI53C810A.

 

Table 7.16

PCI Timing

 

 

 

 

 

 

 

 

Symbol

Parameter

Min

Max

Unit

 

 

 

 

 

t1

Shared signal input setup time

7

ns

 

 

 

 

 

t2

Shared signal input hold time

ns

t3

CLK to shared signal output valid

11

ns

t4

Side signal input setup time

10

ns

t5

Side signal input hold time

ns

t6

CLK to side signal output valid

12

ns

t7

CLK high to FETCH/ low

20

ns

t8

CLK high to FETCH/ high

20

ns

t9

CLK high to MASTER/ low

20

ns

t10

CLK high to MASTER/ high

20

ns

7-26

Electrical Characteristics

Page 208
Image 208
LSI 53C810A technical manual PCI Interface Timing, PCI Timing