I

I/O bit 5-25

I/O instructions 6-13I_O bit 5-18

IARB bit 5-7IDSEL 4-7

IID bit 5-22,5-44

illegal instruction detected bit 5-22,5-44immediate arbitration bit 5-7initialization device select 4-7

initiator mode

phase mismatch 5-51initiator ready 4-7

input 4-3instructions

block move 6-5I/O 6-13

load and store 6-39memory move 6-36read/write 6-23transfer control 6-27

interrupt line 3-18

pin (IP[7:0]) 3-18interrupt status register 5-26interrupt-on-the-fly bit 5-28interrupts

fatal vs. nonfatal interrupts 2-18halting 2-20

IRQ disable bit 2-17,5-46masking 2-18

polling vs. hardware 2-15registers 2-16

stacked interrupts 2-19INTF bit 5-28

IRDY/ 4-7

IRQ disable bit 5-46IRQ mode bit 5-46IRQD bit 5-46IRQM bit 5-46ISTAT register 5-26

L

last disconnect bit 5-25latched SCSI parity bit 5-24latency

timer (LT[7:0]) 3-16LDSC bit 5-25

LOA bit 5-23

load and store instructions 6-39no flush option 6-40

prefetch unit and store instructions 2-4,6-41lost arbitration bit 5-23

LOW bit 5-63

LSI53C700 family compatibility bit 5-47LSI53C810A

ease of use 1-4flexibility 1-5integration 1-4performance 1-3reliability 1-5testability 1-6

M

M/A bit 5-48,5-51MACNTL register 5-55MAN bit 5-43

manual start mode bit 5-43MASR bit 5-37

master control for set or reset pulses bit 5-37master data parity error bit 5-21

MDPE bit 5-44master enable bit 5-56

master parity error enable bit 5-35max SCSI synchronous offset bits 5-14max_lat (ML[7:0]) 3-19

MDPE bit 5-21

memory access control register 5-55memory move instructions 6-36

and SCRIPTS instruction prefetching 2-3no flush option 6-38

memory read line command 3-6memory read multiple command 3-7memory write and invalidate command 3-5

write and invalidate mode bit 3-12min_gnt (MG[7:0]) 3-19

move to/from SFBR cycles 6-24MPEE bit 5-35

MSG bit 5-18,5-20,5-25

N

NFMMOV instruction 6-38

no flush memory-to-memory move 6-38

O

OLF bit 5-23

opcode fetch bursting 2-4operating registers

adder sum output 5-47chip test five 5-36chip test four 5-34chip test one 5-30chip test six 5-37chip test three 5-32chip test two 5-30chip test zero 5-29

data structure address 5-26DMA byte counter 5-38DMA command 5-39DMA control 5-45

DMA FIFO 5-33

DMA interrupt enable 5-44DMA mode 5-41

DMA next address 5-39DMA SCRIPTS pointer 5-39DMA SCRIPTS pointer save 5-40DMA status 5-20

general information 5-1general purpose 5-16

general purpose pin control 5-56interrupt status 5-26

memory access control 5-55response ID zero 5-59scratch register A 5-41SCSI bus control lines 5-20

Index

IX-3

Page 225
Image 225
LSI 53C810A technical manual Index