LSI 53C810A technical manual Register 0x4C 0xCC, Ssaid, Slt, Art, Soz

Register: 0x4C (0xCC)

SCSI Test Zero (STEST0)

Read Only

7		6			4	3	2	1	0
	R			SSAID		SLT	ART	SOZ	SOM
	x	x		x	x	0	x	1	1
R			Reserved						7
SSAID			SCSI Selected As ID						[6:4]
			These bits contain the encoded value of the SCSI ID that
			the LSI53C810A is selected or reselected as during a
			SCSI selection or reselection phase. These bits are read
			only and contain the encoded value of 0–7 possible IDs
			that could be used to select the LSI53C810A. During a
			SCSI selection or reselection phase, when a valid ID has
			been put on the bus, and the LSI53C810A responds to
			that ID, the “selected as” ID is written into these bits.
SLT			Selection Response Logic Test						3
			This bit is set when the LSI53C810A is ready to be
			selected or reselected. This does not take into account
			the bus settle delay of 400 ns. This bit is used for
			functional test and fault purposes.
ART			Arbitration Priority Encoder Test						2
			This bit is always set when the LSI53C810A exhibits the
			highest priority ID asserted on the SCSI bus during
			arbitration. It is primarily used for chip level testing, but it
			may be used during low level mode operation to
			determine if the LSI53C810A won arbitration.
SOZ			SCSI Synchronous Offset Zero						1
			This bit indicates that the current synchronous
			SREQ/SACK offset is zero. This bit is not latched and
			may change at any time. It is used in low level
			synchronous SCSI operations. When this bit is set, the
			LSI53C810A functioning as an initiator, is waiting for the
			target to request data transfers. If the LSI53C810A is a
			target, then the initiator has sent the offset number of
			acknowledges.

5-60 Operating Registers