LSI 53C810A - page 158

6-18 Instruction Set of the I/O Processor

ﬁeldstored in the DMA Next Address (DNAD) register.

Manually set the LSI53C810A to Initiator mode if it is

reselected, or to Targetmode if it is selected.

4. If the Select with SATN/ﬁeld is set, the SATN/ signal

is asserted during the selection phase.

Wait Disconnect Instruction

1. The LSI53C810A waits for the Targetto perform a

“legal” disconnect from the SCSI bus. A “legal”

disconnect occurs when SBSY/ and SSEL/ are

inactive for a minimum of one Bus Free delay

(400 ns), after the LSI53C810A has received a

Disconnect Message or a Command Complete

Message.

Wait Reselect Instruction

1. If the LSI53C810A is selected before being

reselected, it fetches the next instruction from the

address pointed to by the 32-bit jump address ﬁeld

stored in the DMA Next Address (DNAD) register.

Manually set the LSI53C810A to Targetmode when it

is selected.

2. If the LSI53C810A is reselected, it fetches the next

instruction from the address pointed to by the DMA

SCRIPTS Pointer (DSP) register.

3. If the CPU sets the SIGP bit in the Interrupt Status

(ISTAT)register, the LSI53C810A aborts the Wait

Reselect instruction and fetches the next instruction

from the address pointed to by the 32-bit jump

addressﬁeld stored in the DMA Next Address (DNAD)

register.

Set Instruction

When the SACK/ or SATN/bits are set, the

corresponding bits in the SCSI Output Control Latch

(SOCL) register are set. When the target bit is set, the

corresponding bit in the SCSI Control Zero (SCNTL0)

register is also set. When the Carry bit is set, the

corresponding bit in the ALU is set.

Contents

Main ii Preface (SCSI-3 Parallel Interface) SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor SCSI: Understanding the Small Computer System Interface SCSI SCRIPTS Processors Programming Guide, assert deassert Page Contents Page Page Page Page Page Chapter 1 General Description 1.1 TolerANTTechnology 1.2 LSI53C810A Benets Summary 1.2.1 SCSI Performance 1.2.2 PCI Performance 1.2.3 Integration 1.2.4 Ease of Use 1.2.5 Flexibility 1.2.6 Reliability 1.2.7 Testability LSI53C810A Benets Summary 1-7 Figure 1.1 LSI53C810A System Diagram 1-8 General Description Figure 1.2 LSI53C810A Chip Block Diagram Chapter 2 Functional Description 2.1 SCSI Core 2.1.1 DMA Core 2.2 SCRIPTS Processor 2.2.1 SDMS Software: The Total SCSI Solution 2.3 Prefetching SCRIPTS Instructions 2.3.1 Opcode Fetch Burst Capability 2.4 PCI Cache Mode 2.4.1 Load and Store Instructions 2.4.2 3.3 V/5 V PCI Interface 2.4.3 Loopback Mode SCSI SCRIPTS Processors Programming Guide 2.5 Parity Options 2-6 Functional Description Table 2.1 Bits Used for Parity Control and Observation Parity Options 2-7 Table 2.2 SCSI Parity Control Table 2.3 SCSI Parity Errors and Interrupts 2.5.1 DMA FIFO Page Page 2.6 SCSI Bus Interface 2.6.1 TerminatorNetworks 2.6.2 Select/Reselect During Selection/Reselection 2-12 Functional Description 2.6.3 Synchronous Operation Page Interrupt Handling 2-15 Figure 2.4 Determining the Synchronous TransferRate 2.7 Interrupt Handling 2.7.1 Polling and Hardware Interrupts Page Page Page Page Page Page Page Chapter 3 PCI Functional Description 3.1 PCI Addressing 3.1.1 Conguration Space 3.1.2 PCI Bus Commands and Functions Supported 3.2 PCI Cache Mode 3.2.1 Support for PCI Cache Line Size Register 3.2.2 Selection of Cache Line Size 3.2.3 Alignment Page Page 3.2.4 Memory Read Multiple Command 3.2.5 Unsupported PCI Commands 3.3 Conguration Registers Page Register: 0x00 Register: 0x02 Register: 0x04 Page Register: 0x06 Page Register: 0x08 Register: 0x09 Register: 0x0C Register: 0x0D Register: 0x0E Register: 0x10 Register: 0x14 Register: 0x3C Register: 0x3D Register: 0x3E Register: 0x3F Page Page 4-2 Signal Descriptions Figure 4.1 LSI53C810A Pin Diagram Quad Flat Pack LSI53C810A 100-pin 4-3 Signals are assigned a type. There are four signal types: Table4.1 describes the Power and Ground Signals group. Table 4.1 Power and Ground Signals 4-4 Signal Descriptions Figure 4.2 Functional Signal Grouping 4.1 PCI Bus Interface Signals 4.1.1 System Signals 4-6 Signal Descriptions 4.1.2 Address and Data Signals Table4.3 describes the Address and Data Signals group. Table 4.3 Address and Data Signals PCI Bus Interface Signals 4-7 4.1.3 Interface Control Signals Table4.4 describes the Interface Control Signals group. Table 4.4 Interface Control Signals 4.1.4 Arbitration Signals 4.1.5 Error Reporting Signals SCSI Bus Interface Signals 4-9 4.2 SCSI Bus Interface Signals 4.2.1 SCSI Bus Interface Signals Table4.7 describes the SCSI Bus Interface Signals group. Table 4.7 SCSI Bus Interface Signals 4-10 Signal Descriptions 4.2.2 Additional Interface Signals Table4.8 describes the Additional Interface Signals group. Table 4.8 Additional Interface Signals SCSI Bus Interface Signals 4-11 Table 4.8 Additional Interface Signals (Cont.) Page Chapter 5 Operating Registers 5-2 Operating Registers Figure 5.1 Register Address Map Register: 0x00 (0x80) SCSI Control Zero (SCNTL0) Read/Write Page Page Page Register: 0x01 (0x81) Page Page Register: 0x02 (0x82) Register: 0x03 (0x83) Page Register: 0x04 (0x84) Register: 0x05 (0x85) 5-13 Table 5.3 Examplesof Synchronous Transfer Periods and Rates for SCSI-1 5-14 Operating Registers Table 5.3 Examplesof Synchronous Transfer Periods and Rates for SCSI-1 (Cont.) Table 5.4 Examplesof Synchronous Transfer Periods and Rates for Fast SCSI Register: 0x06 (0x86) Register: 0x07 (0x87) Register: 0x08 (0x88) Register: 0x09 (0x89) Register: 0x0A (0x8A) Register: 0x0B (0x8B) Register: 0x0C (0x8C) Page Register: 0x0D (0x8D) Page Register: 0x0E (0x8E) Register: 0x0F (0x8F) Registers:0x100x13 (0x900x93) Register: 0x14 (0x94) Page Register: 0x18 (0x98) Register: 0x19 (0x99) Register: 0x1A (0x9A) Page Register: 0x1B (0x9B) Registers:0x1C0x1F (0x9C0x9F) Register: 0x20 (0xA0) Register: 0x21 (0xA1) Page Register: 0x22 (0xA2) Register: 0x23 (0xA3) Registers:0x240x26 (0xA40xA6) Register: 0x27 (0xA7) Registers:0x280x2B (0xA80xAB) Registers:0x2C0x2F (0xAC0xAF) Registers:0x300x33 (0xB00xB3) Registers:0x340x37 (0xB40xB7) Register: 0x38 (0xB8) Page Page Register: 0x39 (0xB9) Register: 0x3A (0xBA) Register: 0x3B (0xBB) Page Register: 0x3C0x3F (0xBC0xBF) Register: 0x40 (0xC0) Page Register: 0x41 (0xC1) Register: 0x42 (0xC2) Page Register: 0x43 (0xC3) Register: 0x44 (0xC4) Register: 0x46 (0xC6) Register: 0x47 (0xC7) Register: 0x48 (0xC8) Register: 0x49 (0xC9) Register: 0x4A (0xCA) Register: 0x4C (0xCC) Register: 0x4D (0xCD) Register: 0x4E (0xCE) Register: 0x4F (0xCF) Page Register: 0x50 (0xD0) Registers:0x54 (0xD4) Registers:0x58 (0xD8) Chapter 6 Instruction Set of the I/O Processor 6.1 Low Level Register Interface Mode 6.2 SCSI SCRIPTS 6.2.1 Sample Operation Page 6.3 Block Move Instructions B 6.3.1 First Dword Page Page Page Page Page 6.3.2 Second Dword 6.4 I/O Instruction 6.4.1 First Dword Page Page 6-16 Instruction Set of the I/O Processor Page Page Page Page Page 6.4.2 Second Dword 6.5 Read/Write Instructions 6.5.1 First Dword 6.5.2 Second Dword 6.5.3 Read-Modify-Write Cycles 6.5.4 Move To/From SFBR Cycles Read/Write Instructions 6-25 6-26 Instruction Set of the I/O Processor Table 6.2 Read/Write Instructions 6.6 Transfer Control Instructions 6.6.1 First Dword Page Page 6-30 Instruction Set of the I/O Processor Page Page Page Page Page 6.7 Memory Move Instructions Page 6.7.1 First Dword 6.7.2 Second Dword 6.7.3 Third Dword 6.7.4 Read/Write System Memory from a SCRIPTS Instruction 6.8 Load and Store Instructions 6.8.1 First Dword 6.8.2 Second Dword 6-42 Instruction Set of the I/O Processor Chapter 7 Electrical Characteristics 7.1 DC Characteristics 7-2 Electrical Characteristics Table 7.1 Absolute Maximum Stress Ratings Table 7.2 Operating Conditions Table 7.3 SCSI SignalsSD[7:0]/, SDP/, SREQ/, SACK/ Table 7.4 SCSI SignalsSMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/ Table 7.5 Input SignalsCLK, SCLK, GNT/, IDSEL, RST/, TESTIN 7-4 Electrical Characteristics Table 7.6 Capacitance Table 7.7 Output SignalsMAC/_TESTOUT,REQ/ Table 7.8 Output SignalIRQ/ DC Characteristics 7-5 Table 7.9 Output SignalSERR/ 7.2 TolerANT Technology TolerANTTechnology 7-7 Table 7.12 TolerANT TechnologyElectrical Characteristics 7-8 Electrical Characteristics Figure 7.1 Rise and Fall Time Test Conditions Figure 7.2 SCSI Input Filtering Figure 7.3 Hysteresis of SCSI Receiver TolerANTTechnology 7-9 Figure 7.4 Input Current as a Function of Input Voltage Figure 7.5 Output Current as a Function of Output Voltage 7-10 Electrical Characteristics 7.3 AC Characteristics Figure 7.6 Clock Timing Table 7.13 Clock Timing AC Characteristics 7-11 Table7.14 and Figure 7.7 provide reset input timing data. Figure 7.7 Reset Input Figure 7.8 Interrupt Output Waveforms Table7.15 and Figure 7.8 provide interrupt output timing data. Table 7.14 ResetInput Timing 7.4 PCI Interface Timing Diagrams Target Timing Initiator Timing PCI Interface Timing Diagrams 7-13 7.4.1 Target Timing Figure 7.9 through Figure 7.12 describe target timing. Figure 7.9 PCI Conguration Register Read 7-14 Electrical Characteristics Figure 7.10 PCI Conguration Register Write PCI Interface Timing Diagrams 7-15 Figure 7.11 Target Read 7-16 Electrical Characteristics Figure 7.12 Target Write PCI Interface Timing Diagrams 7-17 7.4.2 Initiator Timing Figure 7.13 through Figure 7.18 describe initiator timing. Figure 7.13 OpCodeFetch, Nonburst 7-18 Electrical Characteristics Figure 7.14 Burst Opcode Fetch PCI Interface Timing Diagrams 7-19 Figure 7.15 Back-to-Back Read 7-20 Electrical Characteristics Figure 7.16 Back-to-Back Write Page 7-22 Electrical Characteristics Figure 7.17 Burst Read PCI Interface Timing Diagrams 7-23 Figure 7.17 Burst Read (Cont.) 7-24 Electrical Characteristics Figure 7.18 Burst Write PCI Interface Timing Diagrams 7-25 Figure 7.18 Burst Write (Cont.) 7-26 Electrical Characteristics 7.5 PCI Interface Timing Table7.16 describes the PCI timing data for the LSI53C810A. Table 7.16 PCI Timing SCSI Timings 7-27 7.6 SCSI Timings Tables7.17 through 7.23 and Figures 7.19 through 7.23 describe the LSI53C810A SCSI timing data. Figure 7.19 Initiator Asynchronous Send Table 7.17 Initiator Asynchronous Send (5 Mbytes/s) Figure 7.20 Initiator Asynchronous Receive 7-28 Electrical Characteristics Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s) Figure 7.21 Target Asynchronous Send SCSI Timings 7-29 Table 7.19 Target AsynchronousSend (5 Mbytes/s) 7-30 Electrical Characteristics Figure 7.22 Target Asynchronous Receive Figure 7.23 Initiator and TargetSynchronous Transfers Table 7.20 Target AsynchronousReceive (5 Mbytes/s) SCSI Timings 7-31 Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s) Table 7.22 SCSI-2 Fast Transfers(10.0 Mbytes/s (8-Bit Transfers), 40 MHz Clock) 7-32 Electrical Characteristics Table 7.23 SCSI-2 Fast Transfers(10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock) Page Page Page Page LSI53C810A PCI to SCSI I/O Processor A-1 Appendix A Register Summary A-2 Register Summary TableA.2 lists the LSI53C810A SCSI registers by register name. TableA.2 SCSI Registers Register Summary A-3 TableA.2 SCSI Registers Page LSI53C810A PCI to SCSI I/O Processor IX-1 Index Symbols Numerics A B D E F G H I L M N O P R Index IX-5 IX-6 Index S Index IX-7 IX-8 Index T U V W Z Customer Feedback LSI53C810A PCI to SCSI I/O Processor TechnicalManual. U.S. Distributors by State U.S. Distributors by State (Continued) Direct Sales Representatives by State (Component and Boards) Sales Ofces and Design Resource Centers International Distributors