7.4.2 Initiator Timing

Figure 7.13 through Figure 7.18 describe initiator timing.

Figure 7.13 OpCode Fetch, Nonburst

CLK

 

 

(Driven by System)

 

 

GPIO0_FETCH/

t7

t8

(Driven by LSI53C810A)

 

 

GPIO1_MASTER/

t9

t10

 

 

(Driven by LSI53C810A)

 

 

REQ/

t6

 

 

 

(Driven by LSI53C810A)

 

 

GNT/ (Driven by Arbiter)

FRAME/ (Driven by LSI53C810A)

t4

 

t5

 

t3

t1

Data

Data

In

In

AD/ (Driven by LSI53C810A- Addr; Target-Data)

C_BE/ (Driven by LSI53C810A)

PAR/ (Driven by LSI53C810A- Addr/ Target-Data)

IRDY/ (Driven by LSI53C810A)

Addr

Out

t3

CMD

BE

t3

t3

t3

Addr

Out

t2

CMD BE

t1

t2

TRDY/ (Driven by Target)

STOP/ (Driven by Target)

DEVSEL/ (Driven by Target)

t3

t1

 

 

t2

 

t2

 

t1

PCI Interface Timing Diagrams

7-17

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Image 199
LSI 53C810A technical manual OpCode Fetch, Nonburst