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LSI 53C810A technical manual Register 0x0B 0x8B, Register 0x0C 0x8C

Models: 53C810A

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Register: 0x0B (0x8B)

SCSI Bus Control Lines (SBCL)

Read Only

7	6	5			4	3	2	1	0
REQ	ACK		BSY		SEL	ATN	MSG	C/D	I/O

x	x		x		x	x	x	x	x

REQ		SREQ/ Status							7
ACK		SACK/ Status							6
BSY		SBSY/ Status							5
SEL		SSEL/ Status							4
ATN		SATN/ Status							3
MSG		SMSG/ Status							2
C/D		SC_D/ Status							1
I/O		SI_O/ Status							0

This register returns the SCSI control line status. A bit is set when the corresponding SCSI control line is asserted. These bits are not latched; they are a true representation of what is on the SCSI bus at the time the register is read. The resulting read data is synchronized before being presented to the PCI bus to prevent parity errors from being passed to the system. This register is used for diagnostics testing or operation in low level mode.

Register: 0x0C (0x8C)

DMA Status (DSTAT)

Read Only

7	6	5	4	3	2	1	0
DFE	MDPE	BF	ABRT	SSI	SIR	R	IID
1	0	0	0	0	0	x	0

Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C810A stacks interrupts). The DIP bit

5-20	Operating Registers

Image 94

LSI 53C810A technical manual Register 0x0B 0x8B, Register 0x0C 0x8C

Contents

Technical Manual R c h 2 0 0Trademark Acknowledgment Audience OrganizationAnsi Conventions Used in This Manual PCI Special Interest GroupRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology LSI53C810A Beneﬁts Summary Scsi PerformanceIntegration PCI PerformanceEase of Use Flexibility ReliabilityTestability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Chapter Functional Description Scsi CoreScripts Processor DMA CoreSdms Software The Total Scsi Solution Prefetching Scripts InstructionsPCI Cache Mode Opcode Fetch Burst CapabilityLoad and Store Instructions Loopback ModeParity Options 2 3.3 V/5 V PCI InterfaceBits Used for Parity Control and Observation BIt Name Location DescriptionScsi Parity Errors and Interrupts Scsi Parity ControlDMA Fifo Data PathsSynchronous Scsi Send Asynchronous Scsi SendAsynchronous Scsi Receive Synchronous Scsi Receive LSI53C810A Host Interface Data PathsTerminator Networks Scsi Bus InterfaceSelect/Reselect During Selection/Reselection Active or Regulated Termination Determining the Data Transfer Rate Synchronous OperationSCNTL3 Register, Bits 64 SCF20 Sxfer Register, Bits 75 TP20 SCNTL3 Register, Bits 20 CCF20Achieving Optimal Scsi Send Rates Interrupt Handling Polling and Hardware InterruptsRegisters Interrupt Handling Fatal vs. Nonfatal Interrupts MaskingStacked Interrupts Halting in an Orderly Fashion Sample Interrupt Service Routine Read Interrupt Status IstatFunctional Description PCI Addressing 1 Conﬁguration Space2.1 I/O Read Command PCI Bus Commands and Functions Supported2.2 I/O Write Command Support for PCI Cache Line Size Register Alignment Selection of Cache Line SizeMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands PCI Bus Commands and Encoding Types Conﬁguration RegistersPCI Conﬁguration Register Map Register EBM EperWIE EMSDPE EISEnable I/O Space0Status Read/Write SSERTA DPRData Parity Reported8Register 0x09 Register 0x08RID Register 0x0D Latency Timer Read/Write LTLatency Timer70Register 0x0C Cache Line Size Read/WriteRegister 0x14 Register 0x0ERegister 0x10 BarzInterrupt Line Read/Write ILInterrupt Line70 Register 0x3CRegister 0x3D Interrupt Pin Read Only IPInterrupt Pin70MinGnt Read Only MGMinGnt70 Register 0x3ERegister 0x3F MaxLat Read Only MLMaxLat70PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Signals are assigned a type. There are four signal types Power and Ground SignalsFunctional Signal Grouping System Signals PCI Bus Interface SignalsSystem Signals Address and Data Signals Address and Data SignalsInterface Control Signals Interface Control SignalsArbitration Signals Arbitration SignalsError Reporting Signals Error Reporting SignalsScsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface SignalsMAC Signal Descriptions Chapter Operating Registers Register 0x00 Scsi Control Zero SCNTL0 Read/WriteSimple Arbitration ARB10 Arbitration Mode Bits 1Full Arbitration, Selection/Reselection Start Sequence StartWatn Select with SATN/ on a Start Sequence4 AAP EPCTRG ADB Register 0x01EXC DHPAesp CONRST IarbSSTStart Scsi Transfer0 Register 0x03 Register 0x02SDU Reserved CCF20 Clock Conversion Factor RRE Register 0x04SRE Scsi Transfer Sxfer Read/Write Register 0x05Reserved ENC20 Encoded LSI53C810A Chip Scsi ID TP20 Scsi Synchronous Transfer Period75TP2 TP1 TP0 Xferp Reserved MO30 Max Scsi Synchronous Offset Sclk SCNTL3Scsi Destination ID Sdid Read/Write Register 0x06Scsi Synchronous Offset Values Reserved ENC20 Encoded destination Scsi IDGeneral Purpose Gpreg Read/Write Register 0x07Reserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write BSY REQACK SELVAL Register 0x0A 0x8AScsi Selector ID Ssid Read Only Scsi Valid BitRegister 0x0B 0x8B Register 0x0C 0x8CAbrt DFEMdpe SSIILF Register 0x0D 0x8DIID ORFLOA OLFAIP WOAFF30 Fifo Flags Register 0x0E 0x8EScsi Status One SSTAT1 Read Only Sdpl Latched Scsi Parity3Scsi Status Two SSTAT2 Read Only Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ SignalRegister 0x0F 0x8F LdscRegisters 0x10-0x13 DSASigp SrstSEM Interrupt-on-the-Fly IntfSipscsi Interrupt Pending1 Chip Test Zero CTEST0 Read/Write Register 0x18Dipdma Interrupt Pending0 FMTByte Empty in DMA FIFO70Register 0x1A 0x9A Register 0x19Ddir Dreq CIOTeop DackFLF Register 0x1B 0x9BCLF Temp Registers 0x1C-0x1F 0x9C-0x9FRegister 0x20 0xA0 DMA Fifo DfifoChip Test Four CTEST4 Read/Write Burst DisableRegister 0x21 0xA1 BdisZSD ZmodSrtm Adck Register 0x22 0xA2Bbck Chip Test Six CTEST6 Read/Write Register 0x23 0xA3Masr Dfdma FIFO70DBC Registers 0x24-0x26 0xA4-0xA6DMA Byte Counter DBC Read/Write DMA Byte Counter 230Registers 0x2C-0x2F 0xAC-0xAF Register 0x27 0xA7Registers 0x28-0x2B 0xA8-0xAB DnadDsps Registers 0x30-0x33 0xB0-0xB3DMA Scripts Pointer Save Dsps Read/Write DMA Scripts Pointer Save 310Register 0x38 0xB8 Registers 0x34-0x37 0xB4-0xB7Scratcha ERLEnable Read Line3 Source I/O Memory EnableDestination I/O Memory Enable SiomBOF Burst Opcode Fetch EnableErmp MANManual Start Mode0Register 0x39 0xB9 SIRRegister 0x3A 0xBA Register 0x3B 0xBBSTD SSMIrqm IrqdAdder Sum Output Adder Read Only Register 0x3C-0x3F 0xBC-0xBFCOM AdderRSL Register 0x40 0xC0CMP SGEUnexpected Disconnect Scsi Reset ConditionUDC PARGEN Register 0x41 0xC1STO HTHScsi Interrupt Status Zero SIST0 Read Only Initiator Mode Phase Mismatch Target Mode SATN/ ActiveRegister 0x42 0xC2 CMPFunction Complete6Transfer Sxfer register Scsi RST/ Received Parity ErrorRegister 0x43 0xC3 Scsi Interrupt Status One SIST1 Read OnlyScsi Longitudinal Parity Slpar Read/Write Handshake-to-Handshake Timer ExpiredRegister 0x44 0xC4 Slpar Scsi Longitudinal Parity70Register 0x46 0xC6 Memory Access Control Macntl Read/WriteTYP30 Chip Type DRD Register 0x47 0xC7DWR PscptRegister 0x48 0xC8 Scsi Timer Zero STIME0 Read/WriteHTH30 Handshake-to-Handshake Timer Period GPIO0ENRegister 0x49 0xC9 Scsi Timer One STIME1 Read/WriteReserved GEN30 General Purpose Timer Period SELSelection Time-Out30Register 0x4A 0xCA Response ID Respid Read/Write Respid Response ID70SLT Register 0x4C 0xCCSsaid ARTSclk Register 0x4D 0xCDSiso ROF Register 0x4E 0xCESCE SLBEXT Register 0x4F 0xCFLOW DSI STRHSC TTMScsi Input Data Latch Sidl Read Only Register 0x50 0xD0Stwscsi Fifo Test Write0 Sidlscsi Input Data Latch150Registers 0x54 0xD4 Registers 0x58 0xD8Low Level Register Interface Mode Chapter Instruction Set ProcessorScsi Scripts Sample Operation Scripts InstructionsInstruction Set of the I/O Processor Block Move Instructions Scripts OverviewIT10 Instruction Type Block Move 3130 Indirect Addressing First DwordDirect Addressing TIA Table Indirect AddressingBlock Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Second DwordStart Address 310 I/O Instruction IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927Reselect Instruction Disconnect InstructionWait Select Instruction Set InstructionI/O Instruction Register Clear Instruction Select InstructionWait Disconnect Instruction Wait Reselect InstructionRelative Addressing Mode TITable Indirect Mode25Table Indirect DirectRelative Endid Set/Clear Satn Set/Clear SackSAStart Address310 Read/Write Instructions Read-Modify-Write CyclesMove To/From Sfbr Cycles Read/Write Register Instruction Read/Write Instructions Byte Received SfbrTransfer Control Instructions Jump Instruction Call InstructionReturn Instruction Instruction Type Transfer Control Interrupt Instruction Interrupt on-the-Fly InstructionJump/Call an Absolute Address RARelative Addressing Mode23Jump/Call a Relative Address JMP Jump If True/FalseWVP DCMJump Address 310 Memory Move Instructions Memory to Memory Move Instruction TC230 Transfer Count Third DwordNo Flush Temp Register 310Load and Store Instructions Read/Write System Memory from a Scripts InstructionDSA Relative IT20 Instruction Type 3129Reserved 2726 No Flush Store instruction only Scripts instruction prefetching, see , Func This bit has no effect unless the Prefetch Enable bitDMA Control Dcntl register is set. For information on Memory/IO Address / DSA Offset 310Load and Store Instruction Format Chapter Electrical Characteristics DC CharacteristicsAbsolute Maximum Stress Ratings Operating ConditionsScsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, Srst Scsi Signals-SD70/, SDP/, SREQ/, SackInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signal-IRQ Output Signals-MAC/TESTOUT, REQCapacitance 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy DEVSEL/, STOP/, PERR/, PAR11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER 12 TolerANT Technology Electrical Characteristics PqfpRise and Fall Time Test Conditions Input Current as a Function of Input Voltage AC Characteristics Clock TimingReset Input 14 Reset Input TimingInterrupt Output Target Timing PCI Interface Timing DiagramsInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Interface Timing PCI TimingScsi Timings 17 Initiator Asynchronous Send 5 Mbytes/s18 Initiator Asynchronous Receive 5 Mbytes/s 20 Initiator Asynchronous Receive19 Target Asynchronous Send 5 Mbytes/s 21 Target Asynchronous Send20 Target Asynchronous Receive 5 Mbytes/s 22 Target Asynchronous Receive21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Symbols NumericsIX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Reader’s Comments Excellent Good Average FairDistributors by State CaliforniaNew York Direct Sales Representatives by State Component and Boards Sales Ofﬁces and Design Resource Centers InternationalInternational Distributors