Chapter 2

Functional Description

Chapter 2 is divided into the following sections:

Section 2.1, “SCSI Core”

Section 2.2, “SCRIPTS Processor”

Section 2.3, “Prefetching SCRIPTS Instructions”

Section 2.4, “PCI Cache Mode”

Section 2.5, “Parity Options”

Section 2.6, “SCSI Bus Interface”

Section 2.7, “Interrupt Handling”

The LSI53C810A contains three functional blocks: the SCSI Core, the DMA Core, and the SCRIPTS Processor. The LSI53C810A is fully supported by the SDMS, a complete software package that supports the LSI Logic product line of SCSI processors and controllers.

2.1 SCSI Core

The SCSI core supports synchronous transfer rates up to 10 Mbytes/s and asynchronous transfer rates up to 7 Mbytes/s on an 8-bit SCSI bus. The SCSI core can be programmed with SCSI SCRIPTS, making it easy to fine tune the system for specific mass storage devices or advanced SCSI requirements.

The SCSI core offers low-level register access or a high-level control interface. Like first generation SCSI devices, the LSI53C810A SCSI core can be accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus can be used in error recovery

LSI53C810A PCI to SCSI I/O Processor

2-1

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LSI 53C810A technical manual Chapter Functional Description, Scsi Core