LSI 53C810A 6.8.2 Second Dword

Load and Store Instructions 6-41
Note: This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL) register is set. For information on
SCRIPTS instruction prefetching, see Chapter 2, “Func-
tional Description.”
LS Load and Store 24
When this bit is set, the instruction is a Load. When
cleared, it is a Store.
R Reserved 23
RA[6:0] Register Address [22:16]
A[6:0] select the register to Load and Store to/from within
the LSI53C810A.
Note: It is not possible to load the SCSI First Byte Received
(SFBR) register, although the SFBR contents may be
stored in another location.
R Reserved [15:3]
BC ByteCount [2:0]
This value is the number of bytes to Load and Store.
6.8.2 Second Dword
Memory/IO Address / DSA Offset [31:0]
This is the actual memory location of where to Load and
Store, or the offset from the Data Structure Address
(DSA) register value.