EPC

Enable Parity Checking

3

 

When this bit is set, the SCSI data bus is checked for odd

 

parity when data is received from the SCSI bus in either

 

the initiator or target mode. If a parity error is detected,

 

bit 0 of the SCSI Interrupt Status Zero (SIST0) register is

 

set and an interrupt may be generated.

 

 

If the LSI53C810A is operating in the initiator mode and

 

a parity error is detected, assertion of SATN/ is optional,

 

but the transfer continues until the target changes phase.

 

When this bit is cleared, parity errors are not reported.

 

R

Reserved

2

AAP

Assert SATN/ on Parity Error

1

 

When this bit is set, the LSI53C810A automatically

 

 

asserts the SATN/ signal upon detection of a parity error.

 

SATN/ is only asserted in the initiator mode. The SATN/

 

signal is asserted before deasserting SACK/ during the

 

 

byte transfer with the parity error. Also set the Enable

 

 

Parity Checking bit for the LSI53C810A to assert SATN/

 

in this manner. A parity error is detected on data received

 

from the SCSI bus.

 

 

If the Assert SATN/ on Parity Error bit is cleared or the

 

 

Enable Parity Checking bit is cleared, SATN/ is not

 

 

automatically asserted on the SCSI bus when a parity

 

 

error is received.

 

TRG

Target Mode

0

 

This bit determines the default operating mode of the

 

 

LSI53C810A. The user must manually set the target or

 

 

initiator mode. This is done using the SCRIPTS language

 

(SET TARGET or CLEAR TARGET). When this bit is set, the

 

chip is a target device by default. When this bit is cleared,

 

the LSI53C810A is an initiator device by default.

 

Note:

Writing this bit while not connected may cause the loss of

 

a selection or reselection due to the changing of target or

 

initiator modes.

 

5-5

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LSI 53C810A technical manual Epc, Aap, Trg