LSI 53C810A 2.5.1 DMA FIFO

2-8 Functional Description
2.5.1 DMA FIFO
The DMA FIFO is divided into four sections, each one byte wide and
20 transfersdeep. The DMA FIFO is illustrated in Figure 2.1.
Figure 2.1 DMA FIFO Sections
2.5.1.1 DataPaths
The data path through the LSI53C810A is dependent on whether data is
being moved into or out of the chip, and whether SCSI data is being
transferred asynchronously or synchronously.
Figure 2.2 shows how data is movedto/from the SCSI bus in each of the
different modes.
The following steps determine if any bytes remain in the data path when
the chip halts an operation:
32-bits Wide
20
Bytes
Deep
8-bits
Byte Lane 1 8-bits
Byte Lane 0
8-bits
Byte Lane 2
8-bits
Byte Lane 3