7.21

Target Asynchronous Send

7-29

7.22

Target Asynchronous Receive

7-30

7.23

Initiator and Target Synchronous Transfers

7-30

7.24

100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)

7-34

 

 

 

Tables

 

 

2.1

Bits Used for Parity Control and Observation

2-6

2.2

SCSI Parity Control

2-7

2.3

SCSI Parity Errors and Interrupts

2-7

3.1

PCI Bus Commands and Encoding Types

3-9

3.2

PCI Configuration Register Map

3-10

4.1

Power and Ground Signals

4-3

4.2

System Signals

4-5

4.3

Address and Data Signals

4-6

4.4

Interface Control Signals

4-7

4.5

Arbitration Signals

4-8

4.6

Error Reporting Signals

4-8

4.7

SCSI Bus Interface Signals

4-9

4.8

Additional Interface Signals

4-10

5.1

Synchronous Clock Conversion Factor

5-10

5.2

Asynchronous Clock Conversion Factor

5-11

5.3

Examples of Synchronous Transfer Periods and

 

 

Rates for SCSI-1

5-13

5.4

Examples of Synchronous Transfer Periods and

 

 

Rates for Fast SCSI

5-14

5.5

SCSI Synchronous Offset Values

5-15

6.1

SCRIPTS Instructions

6-3

6.2

Read/Write Instructions

6-26

7.1

Absolute Maximum Stress Ratings

7-2

7.2

Operating Conditions

7-2

7.3

SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/

7-3

7.4

SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/,

 

 

SSEL/, SRST/

7-3

7.5

Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN

7-3

7.6

Capacitance

7-4

7.7

Output Signals—MAC/_TESTOUT, REQ/

7-4

7.8

Output Signal—IRQ/

7-4

7.9

Output Signal—SERR/

7-5

Contents

xi

Page 11
Image 11
LSI 53C810A technical manual Tables