LSI 53C810A Bits Used for Parity Control and Observation, BIt Name Location Description

Table 2.1	Bits Used for Parity Control and Observation
BIt Name		Location	Description
Assert SATN/ on Parity		SCSI Control	Causes the LSI53C810A to automatically assert SATN/
Errors		Zero (SCNTL0),	when it detects a parity error while operating as an
		Bit 1	initiator.
Enable Parity Checking		SCSI Control	Enables the LSI53C810A to check for parity errors.
		Zero (SCNTL0),	The LSI53C810A checks for odd parity.
		Bit 3
Assert Even SCSI Parity		SCSI Control	Determines the SCSI parity sense generated by the
		One (SCNTL1),	LSI53C810A to the SCSI bus.
		Bit 2
Disable Halt on SATN/ or		SCSI Control	Causes the LSI53C810A not to halt operations when a
a Parity Error (Target		One (SCNTL1),	parity error is detected in target mode.
Mode Only)		Bit 5
Enable Parity Error		SCSI Interrupt	Determines whether the LSI53C810A generates an
Interrupt		Enable Zero	interrupt when it detects a SCSI parity error.
		(SIEN0), Bit 0
Parity Error		SCSI Interrupt	This status bit is set whenever the LSI53C810A
		Status Zero	detects a parity error on the SCSI bus.
		(SIST0), Bit 0
Status of SCSI Parity		SCSI Status Zero	This status bit represents the active HIGH current state
Signal		(SSTAT0), Bit 0	of the SCSI SDP0 parity signal.
Latched SCSI Parity		SCSI Status One	This bit reflects the SCSI odd parity signal
		(SSTAT1), Bit 3	corresponding to the data latched into the SCSI Input
			Data Latch (SIDL) register.
Master Parity Error		Chip Test Four	Enables parity checking during master data phases.
Enable		(CTEST4), Bit 3
Master Data Parity Error		DMA Status	Set when the LSI53C810A, as a PCI master, detects a
		(DSTAT), Bit 6	target device signaling a parity error during a data
			phase.
Master Data Parity Error		DMA Interrupt	By clearing this bit, a Master Data Parity Error does not
Interrupt Enable		Enable (DIEN),	cause assertion of IRQ/, but the status bit is set in the
		Bit 6	DMA Status (DSTAT) register.

2-6 Functional Description