determines the transfer rate. For example, if SCLK is

40 MHz and the SCF value is set to divide by one, then the maximum synchronous receive rate is 10 Mbytes/s ((40/1) /4 = 10).

For synchronous send, the output of this divider gets divided by the transfer period (XFERP) bits in the SCSI Transfer (SXFER) register, and that value determines the transfer rate. For valid combinations of the SCF and XFERP, see Table 5.2.

Table 5.1

Synchronous Clock Conversion Factor

 

 

 

 

 

 

SCF2

 

SCF1

SCF0

Factor Frequency

 

 

 

 

 

 

 

0

 

0

0

SCLK/3

 

 

 

 

 

 

 

0

 

0

1

SCLK/1

 

 

 

 

 

 

 

0

 

1

0

SCLK/1.5

 

 

 

 

 

 

 

0

 

1

1

SCLK/2

 

 

 

 

 

 

 

1

 

0

0

SCLK/3

 

 

 

 

 

 

 

1

 

0

1

Reserved

 

 

 

 

 

 

 

1

 

1

0

Reserved

 

 

 

 

 

 

 

1

 

1

1

Reserved

 

 

 

 

 

 

 

Note:

For additional information on how the synchronous transfer

 

rate is determined, Section 2.6.3, “Synchronous Operation,”

 

page 2-13.

 

R

Reserved

3

CCF[2:0]

Clock Conversion Factor

[2:0]

 

These bits select the frequency of the SCLK for

 

 

asynchronous SCSI operations. The bit encoding is

 

 

displayed in Table 5.2. All other combinations are

 

 

reserved.

 

5-10

Operating Registers

Page 84
Image 84
LSI 53C810A technical manual Reserved CCF20 Clock Conversion Factor