Memory Read Multiple Command | LSI 53C810A guide

If cache mode is enabled, a Read Line command is issued on all read cycles, except opcode fetches, when the following conditions are met:

∙The CLSE (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and ERL (Enable Read Line, bit 3, DMA Mode (DMODE) register) bits are set.

∙The Cache Line Size register must contain a legal burst size value (2, 4, 8 or 16) and that value is less than or equal to the DMA Mode (DMODE) burst size.

∙The number of bytes to be transferred at the time a cache boundary is reached must be equal to or greater than a full cache line size.

∙The chip is aligned to a cache line boundary.

When these conditions are met, the chip issues a Read Line command instead of a Memory Read during all PCI read cycles. Otherwise, it issues a normal Memory Read command.

3.2.4 Memory Read Multiple Command

This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. The LSI53C810A supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled. This mode is enabled by setting bit 2 (ERMP) of the DMA Mode (DMODE) register. The command is issued when certain conditions are met.

If cache mode is enabled, a Read Multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met:

1.The CLSE bit (Cache Line Size Enable, bit 7, DMA Control (DCNTL) register) and the ERMP bit (Enable Read Multiple, bit 2, DMA Mode (DMODE) register) are set.

2.The Cache Line Size register contains a legal burst size value (2, 4, 8 or 16) and that value is less than or equal to the DMA Mode (DMODE) burst size.

3.The number of bytes to be transferred at the time a cache boundary is reached is equal to or greater than the DMA Mode (DMODE) burst size.

4.The chip is aligned to a cache line boundary.

PCI Cache Mode

3-7

Image 49

LSI 53C810A technical manual Memory Read Multiple Command

Contents

R c h 2 0 0 Technical Manual Trademark Acknowledgment Organization Audience Ansi Conventions Used in This Manual PCI Special Interest GroupRevision Record ViPreface Contents Chapter PCI Functional Description Chapter Electrical Characteristics Figures Tables IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR Chapter General Description TolerANT Technology Scsi Performance LSI53C810A Beneﬁts Summary Integration PCI PerformanceEase of Use Reliability Flexibility Testability LSI53C810A System Diagram LSI53C810A Chip Block Diagram Scsi Core Chapter Functional Description DMA Core Scripts Processor Prefetching Scripts Instructions Sdms Software The Total Scsi Solution Opcode Fetch Burst Capability PCI Cache Mode Parity Options Loopback ModeLoad and Store Instructions 2 3.3 V/5 V PCI Interface BIt Name Location Description Bits Used for Parity Control and Observation Scsi Parity Control Scsi Parity Errors and Interrupts Data Paths DMA Fifo Synchronous Scsi Send Asynchronous Scsi SendAsynchronous Scsi Receive LSI53C810A Host Interface Data Paths Synchronous Scsi Receive Terminator Networks Scsi Bus InterfaceSelect/Reselect During Selection/Reselection Active or Regulated Termination Determining the Data Transfer Rate Synchronous OperationSCNTL3 Register, Bits 64 SCF20 Sxfer Register, Bits 75 TP20 SCNTL3 Register, Bits 20 CCF20Achieving Optimal Scsi Send Rates Polling and Hardware Interrupts Interrupt Handling Registers Interrupt Handling Masking Fatal vs. Nonfatal Interrupts Stacked Interrupts Halting in an Orderly Fashion Read Interrupt Status Istat Sample Interrupt Service Routine Functional Description 1 Conﬁguration Space PCI Addressing 2.1 I/O Read Command PCI Bus Commands and Functions Supported2.2 I/O Write Command Support for PCI Cache Line Size Register Alignment Selection of Cache Line SizeMmov Misalignment Memory Write and Invalidate Command Memory Read Line Command Memory Read Multiple Command Unsupported PCI Commands Conﬁguration Registers PCI Bus Commands and Encoding Types PCI Conﬁguration Register Map Register WIE EperEBM EMS Status Read/Write EISEnable I/O Space0DPE SSE DPRData Parity Reported8 RTA Register 0x09 Register 0x08RID Register 0x0C Latency Timer Read/Write LTLatency Timer70Register 0x0D Cache Line Size Read/Write Register 0x10 Register 0x0ERegister 0x14 Barz Register 0x3D Register 0x3CInterrupt Line Read/Write ILInterrupt Line70 Interrupt Pin Read Only IPInterrupt Pin70 Register 0x3F Register 0x3EMinGnt Read Only MGMinGnt70 MaxLat Read Only MLMaxLat70 PCI Functional Description Chapter Signal Descriptions LSI53C810A Pin Diagram Power and Ground Signals Signals are assigned a type. There are four signal types Functional Signal Grouping System Signals PCI Bus Interface SignalsSystem Signals Address and Data Signals Address and Data Signals Interface Control Signals Interface Control Signals Error Reporting Signals Arbitration SignalsArbitration Signals Error Reporting Signals Scsi Bus Interface Signals Scsi Bus Interface SignalsScsi Bus Interface Signals Additional Interface Signals Additional Interface Signals MAC Signal Descriptions Chapter Operating Registers Scsi Control Zero SCNTL0 Read/Write Register 0x00 Simple Arbitration ARB10 Arbitration Mode Bits 1Full Arbitration, Selection/Reselection Start Sequence StartWatn Select with SATN/ on a Start Sequence4 AAP EPCTRG EXC Register 0x01ADB DHP RST CONAesp Iarb SSTStart Scsi Transfer0 Register 0x03 Register 0x02SDU Reserved CCF20 Clock Conversion Factor RRE Register 0x04SRE Reserved ENC20 Encoded LSI53C810A Chip Scsi ID Register 0x05Scsi Transfer Sxfer Read/Write TP20 Scsi Synchronous Transfer Period75 TP2 TP1 TP0 Xferp Sclk SCNTL3 Reserved MO30 Max Scsi Synchronous Offset Scsi Synchronous Offset Values Register 0x06Scsi Destination ID Sdid Read/Write Reserved ENC20 Encoded destination Scsi ID General Purpose Gpreg Read/Write Register 0x07Reserved GPIO10 General Purpose Scsi First Byte Received Sfbr Read/Write ACK REQBSY SEL Scsi Selector ID Ssid Read Only Register 0x0A 0x8AVAL Scsi Valid Bit Register 0x0C 0x8C Register 0x0B 0x8B Mdpe DFEAbrt SSI IID Register 0x0D 0x8DILF ORF AIP OLFLOA WOA Scsi Status One SSTAT1 Read Only Register 0x0E 0x8EFF30 Fifo Flags Sdpl Latched Scsi Parity3 Register 0x0F 0x8F Scsi MSG/ Signal Scsi CD/ Signal Scsi IO/ SignalScsi Status Two SSTAT2 Read Only Ldsc DSA Registers 0x10-0x13 Sigp SrstSEM Interrupt-on-the-Fly IntfSipscsi Interrupt Pending1 Dipdma Interrupt Pending0 Register 0x18Chip Test Zero CTEST0 Read/Write FMTByte Empty in DMA FIFO70 Register 0x1A 0x9A Register 0x19Ddir Teop CIODreq Dack FLF Register 0x1B 0x9BCLF Register 0x20 0xA0 Registers 0x1C-0x1F 0x9C-0x9FTemp DMA Fifo Dfifo Register 0x21 0xA1 Burst DisableChip Test Four CTEST4 Read/Write Bdis ZSD ZmodSrtm Adck Register 0x22 0xA2Bbck Masr Register 0x23 0xA3Chip Test Six CTEST6 Read/Write Dfdma FIFO70 DMA Byte Counter DBC Read/Write Registers 0x24-0x26 0xA4-0xA6DBC DMA Byte Counter 230 Registers 0x28-0x2B 0xA8-0xAB Register 0x27 0xA7Registers 0x2C-0x2F 0xAC-0xAF Dnad DMA Scripts Pointer Save Dsps Read/Write Registers 0x30-0x33 0xB0-0xB3Dsps DMA Scripts Pointer Save 310 Register 0x38 0xB8 Registers 0x34-0x37 0xB4-0xB7Scratcha Destination I/O Memory Enable Source I/O Memory EnableERLEnable Read Line3 Siom Ermp Burst Opcode Fetch EnableBOF MANManual Start Mode0 SIR Register 0x39 0xB9 Register 0x3B 0xBB Register 0x3A 0xBA Irqm SSMSTD Irqd COM Register 0x3C-0x3F 0xBC-0xBFAdder Sum Output Adder Read Only Adder CMP Register 0x40 0xC0RSL SGE UDC Scsi Reset ConditionUnexpected Disconnect PAR STO Register 0x41 0xC1GEN HTH Register 0x42 0xC2 Initiator Mode Phase Mismatch Target Mode SATN/ ActiveScsi Interrupt Status Zero SIST0 Read Only CMPFunction Complete6 Transfer Sxfer register Register 0x43 0xC3 Parity ErrorScsi RST/ Received Scsi Interrupt Status One SIST1 Read Only Register 0x44 0xC4 Handshake-to-Handshake Timer ExpiredScsi Longitudinal Parity Slpar Read/Write Slpar Scsi Longitudinal Parity70 Register 0x46 0xC6 Memory Access Control Macntl Read/WriteTYP30 Chip Type DWR Register 0x47 0xC7DRD Pscpt HTH30 Handshake-to-Handshake Timer Period Scsi Timer Zero STIME0 Read/WriteRegister 0x48 0xC8 GPIO0EN Reserved GEN30 General Purpose Timer Period Scsi Timer One STIME1 Read/WriteRegister 0x49 0xC9 SELSelection Time-Out30 Response ID Respid Read/Write Respid Response ID70 Register 0x4A 0xCA Ssaid Register 0x4C 0xCCSLT ART Sclk Register 0x4D 0xCDSiso SCE Register 0x4E 0xCEROF SLB EXT Register 0x4F 0xCFLOW HSC STRDSI TTM Stwscsi Fifo Test Write0 Register 0x50 0xD0Scsi Input Data Latch Sidl Read Only Sidlscsi Input Data Latch150 Registers 0x58 0xD8 Registers 0x54 0xD4 Chapter Instruction Set Processor Low Level Register Interface Mode Scsi Scripts Scripts Instructions Sample Operation Instruction Set of the I/O Processor Scripts Overview Block Move Instructions IT10 Instruction Type Block Move 3130 Indirect Addressing First DwordDirect Addressing Table Indirect Addressing TIA Block Move Instruction Register OpCode Initiator Mode SCSIP20 Scsi Phase2624 TC230 Transfer Counter230 Second DwordStart Address 310 IT10 Instruction Type I/O Instruction 3130 OPC20 OpCode 2927 I/O Instruction Disconnect Instruction Reselect Instruction Set Instruction Wait Select Instruction I/O Instruction Register Select Instruction Clear Instruction Wait Reselect Instruction Wait Disconnect Instruction TITable Indirect Mode25 Relative Addressing Mode Table Indirect DirectRelative Endid Set/Clear Satn Set/Clear SackSAStart Address310 Read-Modify-Write Cycles Read/Write Instructions Move To/From Sfbr Cycles Read/Write Register Instruction Byte Received Sfbr Read/Write Instructions Transfer Control Instructions Call Instruction Jump Instruction Return Instruction Instruction Type Transfer Control Interrupt on-the-Fly Instruction Interrupt Instruction Jump/Call an Absolute Address RARelative Addressing Mode23Jump/Call a Relative Address Jump If True/False JMP DCM WVP Jump Address 310 Memory Move Instructions Memory to Memory Move Instruction No Flush Third DwordTC230 Transfer Count Temp Register 310 Read/Write System Memory from a Scripts Instruction Load and Store Instructions DSA Relative IT20 Instruction Type 3129Reserved 2726 No Flush Store instruction only DMA Control Dcntl register is set. For information on This bit has no effect unless the Prefetch Enable bitScripts instruction prefetching, see , Func Memory/IO Address / DSA Offset 310 Load and Store Instruction Format DC Characteristics Chapter Electrical Characteristics Operating Conditions Absolute Maximum Stress Ratings Scsi Signals-SMSG, SIO/, SCD/, SATN/, SBSY/, SSEL/, Srst Scsi Signals-SD70/, SDP/, SREQ/, SackInput Signals-CLK, SCLK, GNT/, IDSEL, RST/, Testin Output Signal-IRQ Output Signals-MAC/TESTOUT, REQCapacitance DEVSEL/, STOP/, PERR/, PAR 10 Bidirectional Signals-AD310, CBE/30, FRAME/, IRDY/, Trdy 11 Bidirectional Signals-GPIO0FETCH/, GPIO1MASTER Pqfp 12 TolerANT Technology Electrical Characteristics Rise and Fall Time Test Conditions Input Current as a Function of Input Voltage Clock Timing AC Characteristics Reset Input 14 Reset Input TimingInterrupt Output Target Timing PCI Interface Timing DiagramsInitiator Timing PCI Conﬁguration Register Read 10 PCI Conﬁguration Register Write 11 Target Read 12 Target Write 13 OpCode Fetch, Nonburst 14 Burst Opcode Fetch 15 Back-to-Back Read 16 Back-to-Back Write This page intentionally left blank 17 Burst Read OutIn 18 Burst Write AD Driven by LSI53C810A CBE/ Driven by LSI53C810A PCI Timing PCI Interface Timing 17 Initiator Asynchronous Send 5 Mbytes/s Scsi Timings 20 Initiator Asynchronous Receive 18 Initiator Asynchronous Receive 5 Mbytes/s 21 Target Asynchronous Send 19 Target Asynchronous Send 5 Mbytes/s 22 Target Asynchronous Receive 20 Target Asynchronous Receive 5 Mbytes/s 21 SCSI-1 Transfers SE, 5.0 Mbytes/s Symbol Parameter Min Max Unit Package Drawings Package Drawings 24 100 LD Pqfp UD Mechanical Drawing Sheet 1 24 100 LD Pqfp UD Mechanical Drawing Sheet 2 Electrical Characteristics Appendix a Register Summary Table A.2 Scsi Registers Register Summary Table A.2 Scsi Registers Numerics Symbols IX-2Index Index IX-4Index IX-5 IX-6Index IX-7 IX-8Index Customer Feedback Excellent Good Average Fair Reader’s Comments California Distributors by State New York Direct Sales Representatives by State Component and Boards International Sales Ofﬁces and Design Resource Centers International Distributors