Step 2. Read bit 7 in the SCSI Status Zero (SSTAT0) register to determine if any bytes are left in the SCSI Input Data Latch (SIDL) register. If bit 7 is set in SSTAT0, then the SCSI Input Data Latch (SIDL) register is full.

Synchronous SCSI Receive –

Step 1. Subtract the seven least significant bits of the DMA Byte Counter (DBC) register from the 7-bit value of the DMA FIFO (DFIFO) register. AND the result with 0x7F for a byte count between zero and 80.

Step 2. Read the SCSI Status One (SSTAT1) register and examine bits [7:4], the binary representation of the number of valid bytes in the SCSI FIFO, to determine if any bytes are left in the SCSI FIFO.

Figure 2.2 LSI53C810A Host Interface Data Paths

PCI

Interface

PCI

Interface

PCI

Interface

PCI

Interface

DMA FIFO

(4-bytes x 20)

SODL Register

SCSI Interface

Asynchronous

SCSI Send

DMA FIFO

(4-bytes x 20)

SIDL Register

SCSI Interface

Asynchronous SCSI Receive

DMA FIFO

(4-bytes x 20)

SODL Register

SODR Register

SCSI Interface

Synchronous

SCSI Send

DMA FIFO

(4-bytes x 20)

SCSI FIFO

SCSI Interface

Synchronous SCSI Receive

2-10

Functional Description

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LSI technical manual Synchronous Scsi Receive, LSI53C810A Host Interface Data Paths