TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999
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| Terminal Functions (Continued) | |||||||||
host DIO interface |
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| TERMINAL | I/O | INTERNAL |
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| DESCRIPTION | |||||||
| NAME | NO. | RESISTOR |
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| SAD1 | 143 |
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I | Pullup | DIO address bus. SAD1 and SAD0 select the internal host registers, when SDMA is high. | |||||||||||||||
| SAD0 | 142 | |||||||||||||||
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| 138 | I | Pullup | DIO chip select. When low, |
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| indicates a DIO port access is valid. | ||||||
| SCS |
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| SCS | ||||||||||||
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| DIO DMA select. When low, |
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| modifies the behavior of the DIO interface to allow it to operate | ||||
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| SDMA | |||||||||
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| with an external DMA controller. The SAD0 and SAD1 terminals are not used to select the internal | |||||||||
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| host register for the access. Instead, the DIO address to access is provided by the DMA address | |||||||||
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| register, and one of two host register addresses is selected according to DMAinc in the Syscontrol | |||||||||
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| 123 | I | Pullup | register. | ||||||||||
| SDMA |
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| ± If DMAinc = 1, accesses are the DIOdatainc register and DMAaddress increments after each | |||||||||
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| access. | |||||||||
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| ± If DMAinc = 0, accesses are the DIOdata register, and DMAaddress does not increment after | |||||||||
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| each address. | |||||||||
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| SDATA7 | 136 |
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| SDATA6 | 135 |
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| SDATA5 | 133 |
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| DIO data interface bus | ||||||||||||
| SDATA4 | 131 | I/O | Pullup | |||||||||||||
| SDATA3 | 130 | SDATA0 is the least significant bit. | ||||||||||||||
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| SDATA2 | 129 |
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| SDATA1 | 127 |
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| SDATA0 | 126 |
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| SINT | 140 | O | None | DIO interrupt line (interrupt to the attached microprocessor). The interrupt originating event is | ||||||||||||
| stored in the Int register. | ||||||||||||||||
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| DIO ready signal | |||||||||
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| 139 | O | Pullup | ± When low during reads, | SRDY | indicates to the host when data is valid to be read. | |||||||
| SRDY | ||||||||||||||||
| ± When low during writes, SRDY indicates when data has been received after SCS is taken | ||||||||||||||||
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| high. SRDY is driven high for one clock cycle before placing the output in high impedance. | |||||||||
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| DIO read not write | |||||||||
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| 125 | I | Pullup |
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| SRNW |
| ± When high, read operation is selected. | ||||||||||||||
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| ± When low, write operation is selected. | |||||||||
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| Network management port, receive ready. When high, SRXRDY indicates that the network | |||||||||
| SRXRDY | 145 | O | None | management port's RX buffers are empty and the network management port is able to receive | ||||||||||||
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| a frame. | |||||||||
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| Network management port, transmit ready. STXRDY indicates that at least one frame buffer is | |||||||||
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| available to be read by the management CPU. | |||||||||
| STXRDY | 144 | O | None | ± It outputs as a 1 if any of the | ||||||||||||
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| bits in NMTxcontrol is set to 1. | |||||||||
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| ± Otherwise, it outputs 0. | |||||||||
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10 | POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |