Texas Instruments TNETX3270 specifications Host DIO interface

Page 10

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

 

 

 

 

 

 

 

 

Terminal Functions (Continued)

host DIO interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

I/O

INTERNAL

 

 

 

 

 

 

DESCRIPTION

 

NAME

NO.

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SAD1

143

 

 

 

 

 

 

 

 

 

 

 

I

Pullup

DIO address bus. SAD1 and SAD0 select the internal host registers, when SDMA is high.

 

SAD0

142

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

138

I

Pullup

DIO chip select. When low,

 

 

indicates a DIO port access is valid.

 

SCS

 

 

 

SCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIO DMA select. When low,

 

 

 

 

modifies the behavior of the DIO interface to allow it to operate

 

 

 

 

 

 

 

 

SDMA

 

 

 

 

 

 

 

 

with an external DMA controller. The SAD0 and SAD1 terminals are not used to select the internal

 

 

 

 

 

 

 

 

host register for the access. Instead, the DIO address to access is provided by the DMA address

 

 

 

 

 

 

 

 

register, and one of two host register addresses is selected according to DMAinc in the Syscontrol

 

 

 

 

123

I

Pullup

register.

 

SDMA

 

 

 

 

 

 

 

 

 

 

± If DMAinc = 1, accesses are the DIOdatainc register and DMAaddress increments after each

 

 

 

 

 

 

 

 

access.

 

 

 

 

 

 

 

 

± If DMAinc = 0, accesses are the DIOdata register, and DMAaddress does not increment after

 

 

 

 

 

 

 

 

each address.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SDATA7

136

 

 

 

 

 

 

 

 

 

 

 

 

SDATA6

135

 

 

 

 

 

 

 

 

 

 

 

 

SDATA5

133

 

 

DIO data interface bus (byte-wide bidirectional DIO port). SDATA7 is the most significant bit and

 

SDATA4

131

I/O

Pullup

 

SDATA3

130

SDATA0 is the least significant bit.

 

 

 

 

SDATA2

129

 

 

 

 

 

 

 

 

 

 

 

 

SDATA1

127

 

 

 

 

 

 

 

 

 

 

 

 

SDATA0

126

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SINT

140

O

None

DIO interrupt line (interrupt to the attached microprocessor). The interrupt originating event is

 

stored in the Int register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIO ready signal

 

 

 

 

 

 

 

 

 

 

 

 

 

 

139

O

Pullup

± When low during reads,

SRDY

indicates to the host when data is valid to be read.

 

SRDY

 

± When low during writes, SRDY indicates when data has been received after SCS is taken

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

high. SRDY is driven high for one clock cycle before placing the output in high impedance.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIO read not write

 

 

125

I

Pullup

 

 

SRNW

 

± When high, read operation is selected.

 

 

 

 

 

 

 

 

± When low, write operation is selected.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Network management port, receive ready. When high, SRXRDY indicates that the network

 

SRXRDY

145

O

None

management port's RX buffers are empty and the network management port is able to receive

 

 

 

 

 

 

 

 

a frame.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Network management port, transmit ready. STXRDY indicates that at least one frame buffer is

 

 

 

 

 

 

 

 

available to be read by the management CPU.

 

STXRDY

144

O

None

± It outputs as a 1 if any of the end-of-frame (EOF) bits, start-of-frame (SOF) bits, or one of the

 

 

 

 

 

 

 

 

bits in NMTxcontrol is set to 1.

 

 

 

 

 

 

 

 

± Otherwise, it outputs 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Dclk Sdram interfaceDras Dcas DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN5QID VLAN4QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN7QID VLAN6QIDVLAN21QID VLAN20QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN23QID VLAN22QIDFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port Tpid TCI Vlan IDFCS CRCGiant long frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Short framesTransmit control Receive filtering of framesData transmission Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom Load OutcomesHighz instruction Jtag interfaceJtag Instruction Opcodes LED interfaceLamp test Hardware configurationsLED Status Bit Definitions and Shift Order Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalM06TXD Port CLK Sync TXD3M03TXD M04TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s MAC interfaces ports 24±26 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Terminals Sdram Terminal Function TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Held Sdram Terminal Terminal FunctionInitialization TNETX3270 State Terminal During ResetSDRAM-type and quantity indication RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure Dclk TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyThRESET Hold time Low after Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice