Texas Instruments TNETX3270 specifications Network management port

Page 19

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

network management port

Frames can be received or transmitted via the DIO interface using a built-in port, the network management (NM) port.

Frames originating within the host are written to this port via the NMRxcontrol and NMdata registers. Once a frame has been fully written, it is then received by the switch and routed to the destination port(s).

Frames that were routed to this port from any of the switch's ports queue until the host is ready to read them via the NMTxcontrol and NMdata registers. They are then effectively transmitted out of the switch.

IEEE Std 802.1Q VLAN headers on the NM port

Frames received from the host via the NM port are required to contain a valid IEEE Std 802.1Q header. Frames that do not contain a valid header are incorrectly routed. They may be corrupted at the transmission port(s), as the header-stripping process does not verify that the four bytes after the source address are actually a valid header because they always are a valid header under all other circumstances.

When a frame is transmitted to the NM port, no header-stripping occurs, so the frame contains one, or possibly two headers, depending on how the frame was originally received.

full-duplex NM port

The NM port can intermix reception and transmission as desired. The direction of the NMdata access (i.e., read or write) determines whether a byte is removed from the transmit queue or added to the receive queue. The DIO interface is half duplex since it can do only a read or write at one time.

NM bandwidth and priority

The NM port is capable of transferring a byte to or from NMdata once every five cycles, so the burst rate of this port approximates eight bits per 60 ns (or 133 Mbit/s). This can be sustained between the DIO port and the NM port's dedicated transmit or receive buffers.

However, the NM port is prioritized lower than the other ports between its receive and transmit buffers and the external memory system so that at periods of high activity, the NM port does not cause frames to be dropped on the other ports. STXRDY and SRXRDY, the interrupts and freebuffs, EOF, SOF, and interior-of-frame (IOF) mechanisms can be used as desired to prevent unwanted stalls on the DIO bus during busy periods.

The burst rate is unaffected by traffic on other ports.

interrupt processing

There are two interrupts available on the NM port.

The interrupt process uses RXRDY and the nmrx interrupts to indicate when the receive FIFO is empty. This indicates that the NM port is ready to accept a frame of any length (up to 1536 bytes).

If the host needs to download a sequence of frames, it can use the freebuffs field to indicate space availability.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

19

Image 19
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Duplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice