Texas Instruments specifications Eeprom interface, Edio TNETX3270 Eclk SCL SDA, Gnd

Page 27

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

EEPROM interface

The EEPROM interface is provided so the system-level manufacturer can produce a CPU-less, preconfigured system to their customers. Customers also may want to change or reconfigure their system and retain their preferences between system power downs. The device cannot be used without either an EEPROM or CPU connected to it (see Figure 5).

The EEPROM contains configuration and initialization information that are accessed infrequently, typically at power up and after a reset. The organization of the EEPROM data is in accordance with the DIO address map.

EEPROM downloads can be initiated in one of two ways:

DAt the end of hard reset (rising edge on RESET, or completion of a DIO write to DIOaddrhi register that changes the value of the three most significant bits from 010 to another value).

DWriting a 1 to load in Syscontrol register. This bit is cleared automatically when the download completes. It cannot be set during the download by the EEPROM data, thereby preventing a download loop.

During the download, no DIO writes are permitted. If a DIO write is attempted, SRDY is held high until the download has completed.

The EEPROM size is detected automatically according to the address assigned to the EEPROM:

D2048 bits organized as a 256 ⋅ 8 EEPROM should have its A0, A1, and A2 pins tied low.

D8192 bits organized as a 1024 ⋅ 8 EEPROM should have its A0 and A1 pins tied low and A2 pin tied high.

EDIO

TNETX3270

ECLK

SCL

 

 

SDA

 

 

 

24C0x

 

 

 

Flash EEPROM

 

A0

A1

A2

 

 

 

 

 

 

 

24C02 = GND

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

24C08 = VDD

Figure 5. EEPROM Interface Connections

After the initial start condition, a slave address containing a device address of 000 is output on EDIO, and then EDIO is observed for an acknowledge from the EEPROM. If an acknowledge is received, operation continues for the 24C02 EEPROM. If none is received, a stop condition is generated, followed by another start condition and slave address, this time containing a device address of 100. If this receives no acknowledge, no EEPROM is present, and device operation continues, using the current register settings (i.e., those following a hardware reset, or those previously entered by software).

When this device is driving EDIO, it drives out only a strong logic 0. When a logic 1 is intended to be driven out, the pin must be resistively pulled high. An on-chip 50-μA current-source pullup device is provided on this pin. The system designer must decide if this is sufficient to achieve a logic 1 level in a timely manner or if an external supplementary resistor is required.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

27

Page 26 Page 28
Image 27
Page 26 Page 28
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit control Uplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±26Speed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
Top Page Image Contents