Texas Instruments TNETX3270 specifications Pause frame reception

Page 47

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

pause frame reception

The IEEE Std 802.3X standard defines a MAC control frame as any frame containing a length/type value = 88.08 (hex). This device always absorbs (i.e., discards) within the MAC all such frames that it receives, regardless of the configuration of the port (i.e., pause and duplex have no effect on this behavior). MAC control frames are not forwarded to any other port and are not used by IALE for learning source addresses. They appear in the MAC statistics in the same manner as data frames, but are not seen by the IALE, so do not appear in its statistics (i.e., receive filtered frames, security violations, unknown unicast destination, unknown multicast destination, or unknown source).

Pause frames are the subset of MAC control frames with the opcode field = 0x0001. These are acted on by a port only if:

Dpause = 1 in its Portxstatus register

DThe frame's length is 64±1531 bytes, inclusive.

DMxxRXER does not go active at any time during its reception.

DIts FCS passes the CRC.

The pause_time value from such valid frames is extracted from the two bytes following the opcode. This is loaded into the port's pause timer and the pause_time period is timed.

If a valid pause frame is received during the pause_time period of a previous pause frame:

DIf its destination address is not equal to the reserved multicast address or the address in the Devnode register, the pause timer immediately expires.

DIf the new pause_time value is 0, the pause timer immediately expires.

DIf the pause timer within the port immediately is set to the pause_time value of the new pause frame (any remaining pause time from the previous pause frame is disregarded).

If the pause bit in Portxstatus ever becomes a 0 (because pause frames are no longer supported), the pause timer immediately expires.

A port does not begin to transmit any new data frame any later than 512-bit times after a pause frame with a nonzero pause time has been received (RXDV going inactive). It does not begin to transmit any data frame until the pause timer has expired. (However, it can transmit pause frames of its own if it needs to initiate flow control). Any frame already in mid-transmission when a pause frame is received is unaffected; it completes transmission as normal.

pause frame transmission

When the number of free buffers within the switch becomes less than the number specified in Flowthreshold, full-duplex ports that have had pause frames negotiated/enabled transmit a pause frame at the first available opportunity (immediately if currently idle, or following completion of the frame currently being transmitted). The pause frame contains the pausetime field from Pausetimex register that matches the current operating speed of the port.

If the number of free buffers still is less than the number specified in Flowthreshold after 80% of the time interval represented by the respective pausetime field has elapsed, then another pause frame is transmitted at the earliest opportunity.

If the value in Pausetimex is 0, then no pause frames are transmitted on ports with that speed.

It is anticipated that the pausetime values for the different port speeds will be programmed to have a 10:1 ratio, so that different-speed ports pause for the same amount of real time.

Note that transmitted pause frames are only a request to the other end station to stop transmitting. Frames that are received during the pause interval are received normally (provided the buffer memory is not full).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

47

Page 46 Page 48
Image 47
Page 46 Page 48
Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±2610-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
Top Page Image Contents