Texas Instruments TNETX3270 Serial MII management PHY interface, Eeprom interface, Jtag interface

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TNETX3270

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ThunderSWITCH24/3 ETHERNETSWITCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Terminal Functions (Continued)

serial MII management PHY interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

 

 

 

I/O

 

INTERNAL

 

 

 

 

DESCRIPTION

 

 

NAME

 

NO.

 

 

 

 

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MDCLK

121

 

 

O/High Z

 

 

Pullup

Serial MII management data clock. MDCLK can be disabled (high impedance) through the

 

 

 

 

 

 

use of the SIO register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial MII management data I/O. MDIO can be disabled, placed in high Z, through the SIO

 

 

MDIO

120

 

 

 

 

I/O

 

 

Pullup

register. An external 4.7-kΩpullup resistor, conected to VDD(3.3V), is needed to meet the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rise-time requirements.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial MII management reset.

 

 

can be disabled (high impedance) through the use

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MRESET

 

 

MRESET

 

119

 

 

O/High Z

 

 

Pullup

of the SIO register. If connected to a PHY device, an external pullup resistor is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

recommended.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEPROM interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

 

 

INTERNAL

 

 

 

 

 

 

 

DESCRIPTION

 

NAME

NO.

 

 

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ECLK

117

 

O

 

 

 

None

 

 

EEPROM data clock.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEPROM data I/O. An external pulldown resistor may be required for proper operation. Since this

 

 

EDIO

116

 

I/O

 

 

 

Pullup

 

 

terminal has an internal pullup, it can be left unconnected if no EEPROM is present. The EEPROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is optional if a management CPU is present.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LED interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

 

I/O

 

INTERNAL

 

 

 

 

 

DESCRIPTION

 

 

NAME

 

NO.

 

 

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LEDCLK

113

 

 

O

 

None

 

 

LED clock (serial shift clock for the LED status data)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LED data (serial LED status data).

 

 

is active low. All LED information (port link, activity

 

 

 

 

 

114

 

 

O

 

None

 

 

LEDDATA

 

 

LEDDATA

 

 

 

 

 

 

 

 

 

 

status, software status, flow status, and fault status) is sent via this serial interface.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

 

 

INTERNAL

 

 

 

 

 

 

 

DESCRIPTION

 

NAME

NO.

 

 

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCLK

106

 

I

 

 

 

Pullup

 

 

Test clock. TCLK is used to clock state information, test instructions, and test data into and out of the

 

 

 

 

 

 

 

 

device during operation of the test port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

110

 

I

 

 

 

Pullup

 

 

Test data input. TDI is used to serially shift test data and test instructions into the device during

 

 

 

 

 

 

 

 

operation of the test port. An internal pullup resistor is provided on TDI to ensure JTAG compliance.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

108

 

O

 

 

 

None

 

 

Test data output. TDO is used to serially shift test data and test instructions out of the device during

 

 

 

 

 

 

 

 

operation of the test port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test reset.

 

is used for asynchronous reset of the test-port controller. An internal pullup resistor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRST

 

 

TRST

 

111

 

I

 

 

 

Pullup

 

 

is provided to ensure JTAG compliance. If the test port is not used, an external pulldown resistor of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 kΩ may be used to disable the test-port controller.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

107

 

I

 

 

 

Pullup

 

 

Test mode select. TMS is used to control the state of the test-port controller. An internal pullup resistor

 

 

 

 

 

 

 

 

is provided on TMS to ensure JTAG compliance.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Sdram interfaceDras Dcas DclkHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN7QID VLAN6QID VLAN1QID VLAN0QIDVLAN3QID VLAN2QID VLAN5QID VLAN4QIDVLAN23QID VLAN22QID VLAN17QID VLAN16QIDVLAN19QID VLAN18QID VLAN21QID VLAN20QIDFindcontrol Findnode7±0 Findnode15±8 IntenableTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF Findnode23±16 Findnode31±24 Findnode39±32 Findnode47±40Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port CRC Vlan IDFCS Tpid TCIShort frames MII serial management interface PHY managementMbit/s and 10-/100-Mbit/s MAC interface receive control Giant long framesAdaptive performance optimization APO transmit pacing Receive filtering of framesData transmission Transmit controlUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Summary of Eeprom Load Outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Summary of Eeprom load outcomesLED interface Jtag interfaceJtag Instruction Opcodes Highz instructionMulti-LED display Hardware configurationsLED Status Bit Definitions and Shift Order Lamp testTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03COL Port CLK Sync TXD3M03TXD M04TXD M06TXDConnecting to TNETE2008 PHY² 100-Mbit/s Interface Connections 10-/100-Mbit/s port configurationSwitch TNETE2101 Terminal 10-/100-Mbit/s MAC interfaces ports 24±2610-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Held Sdram Terminal Terminal Function Sdram interface TNETX3270 Terminal Interface to SDRAMsSdram Terminals Not Driven by the TNETX3270 Terminals Sdram Terminal Function TNETX3270Refresh TNETX3270 State Terminal During ResetSDRAM-type and quantity indication InitializationIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Dras Dcas TdDA Delay time, from Dclk ↑ to DA InvalidSdram subcycle DclkSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTtOSCIN Transition time, Oscin rise and fall Power-up Oscin and Reset Timing requirements see FigureTsuRESET Setup time Low before Oscin ↑ ThRESET Hold time Low after Oscin ↑Mechanical Data Important Notice
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