Texas Instruments TNETX3270 specifications With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports

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TNETX3270 ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

DPort Configurations: Twenty-Four 10-Mbit/s Ports

±Ports Arranged in Three Groups of Eight Ports in a Multiplexed Interface

±Direct Multiplexer Interface to TNETE2008

±Full and Half Duplex

±Half-Duplex Collision-Based Flow Control

±Full-Duplex IEEE Std 802.3x Flow Control

±Interoperable Support for IEEE Std 802.1Q VLAN

±Speed, Duplex, and Pause

Autonegotiation With Physical Layer (PHY)

Three 10-/100-Mbit/s Ports

±Direct Interface to TNETE2101

±Full and Half Duplex

±Half-Duplex Collision-Based Flow Control

±Full-Duplex IEEE Std 802.3x Flow Control

±Interoperable Support for IEEE Std 802.1Q VLAN

±Pretagging Support

DPort Trunking and Load Sharing

DLED Indication of Port Status

DSDRAM Interface

±Direct Interface to 8-Bit/Word and 16-Bit/Word, 16-Mbit, and 64-Mbit SDRAMs

±32-Bit-Wide Data Bus

±Up to 32 Mbytes Supported

±83.33-MHz SDRAM Clock

±12-ns (±12) SDRAMs Required

DRemote Monitoring (RMON) Support ± Groups 1, 2, 3, and 9

DDirect I/O (DIO) Management Interface

±Eight Bits Wide

±CPU Access to Statistics, Registers, and Management Information Bases (MIBs)

±Internal Network Management Port

±Forwards Spanning-Tree Packets to CPU

±Serial Media-Independent Interface (MII) for PHY Control

DEEPROM Interface for Autoconfiguration (No CPU Required for Nonmanaged Switch)

DInternal Address-Lookup/Frame-Routing Engine

±Interoperable Support for IEEE Std 802.1Q VLAN

±Supports IEEE Std 802.1D Spanning Tree

±Thirty-Two Assignable Virtual LANs (VLANs)

±Multiple Forwarding Modes

±2K Total Addresses Supported

±Port Mirroring

DIEEE Std 1149.1 (JTAG) Interface (3.3-V Signals)

D2.5-V Process With 3.3-V-Drive I/O

DPackaged in 240-Terminal Plastic Quad Flatpack

SDRAM

Controller

EEPROM

Interface

CPU

Interface

TAP

(JTAG)

Queue

Manager

Network

Statistics

Logic

Data Path

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

Controller (MAC)

MUXMUXMUX

Eight Ports (00±07)

10 Mbit/s

Eight Ports (08±15)

10 Mbit/s

Eight Ports (16±23)

10 Mbit/s

Statistics

Storage

MIB

LED

Address

Interface

Compare

 

 

Controller (MAC)

Controller (MAC)

Controller (MAC)

MII

MII

MII

Three Ports (24±26) 10/100 Mbit/s

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI and ThunderSWITCH are trademarks of Texas Instruments Incorporated.

Ethernet is a trademark of Xerox Corporation.

Secure Fast Switching is a trademark of Cabletron Systems, Inc.

Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast Switching.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Eeprom interface Serial MII management PHY interfaceJtag interface Summary of signal terminals by signal group function Power interfaceMiscellaneous Internal Register and Statistics Memory Map DIO register groupsVlan Byte DIO Address Detailed DIO Register MapSIO VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Interface description State of DIO signals during hardware resetReceiving/transmitting management frames Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingTAG Received Pretag Port AssignmentsPort 27 NM Edio TNETX3270 Eclk SCL SDA Eeprom interfaceGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsDuplex Configuration ± MxxFORCEHD Speed Configuration ± MxxFORCE1010-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshVlan support Frame routingIale Ieee Std 802.1Q headers ± reception Address maintenanceIeee Std 802.1Q headers ± transmission Aging algorithms Spanning-tree supportFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink MIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX UnitTiming requirements see Note 7 and Figure 10-/100-Mbit/s MAC interface10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasDIO/DMA write cycle DIO/DMA interfaceSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice
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