Texas Instruments TNETX3270 specifications Miscellaneous, Power interface

Page 12

TNETX3270

ThunderSWITCH24/3 ETHERNETSWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

 

 

 

 

 

 

 

 

 

 

Terminal Functions (Continued)

 

 

miscellaneous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

I/O

 

INTERNAL

 

 

 

 

 

 

DESCRIPTION

 

NAME

NO.

 

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSCIN

112

 

I

 

None

 

Master system clock input (83.33-MHz input clock)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

115

 

I

 

None

 

Reset.

 

 

is synchronous and, therefore, the system clock must be operational during reset.

 

RESET

 

RESET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

power interface

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TERMINAL

 

 

 

 

 

INTERNAL

 

 

 

DESCRIPTION

 

NAME

 

 

 

 

NO.

 

RESISTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8, 14, 34, 40, 55, 68, 74, 81, 88, 94, 100,

 

 

 

 

 

Ground. GND is the 0-V reference for the device. All GND

 

GND

128, 134, 141, 148, 154, 160, 175, 188,

 

 

 

None

 

 

 

 

 

 

terminals must be connected.

 

 

 

 

194, 201, 208, 214, 220, 235

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD(3.3V)

12, 72, 109, 122, 132, 163, 169, 192, 229

 

 

 

None

 

3.3-V supply voltage. Power for the input, output, and I/O

 

 

 

 

 

terminals.

 

 

 

 

 

 

4, 17, 31, 45, 58, 64, 77, 91,

 

 

 

 

 

 

 

 

 

 

 

VDD(2.5V)

 

105, 118, 124, 137, 151, 165, 178,

 

 

 

None

 

2.5-V supply voltage. Power for the core.

 

 

 

 

 

 

184, 197, 211, 225, 238

 

 

 

 

 

 

 

 

 

 

summary of signal terminals by signal group function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT DESCRIPTION

 

NUMBER OF

MULTIPLIER

TOTAL

 

 

 

 

 

 

 

 

 

 

SIGNALS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LED

 

2

 

 

1

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10-Mbit/s port

 

16

 

 

3

48

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10-/100-Mbit/s port

 

19

 

 

3

57

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIO

 

17

 

 

1

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEPROM interface

 

2

 

 

1

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRAM interface

 

50

 

 

1

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Miscellaneous

 

2

 

 

1

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG

 

5

 

 

1

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Serial MII management

 

3

 

 

1

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Total signals

 

 

 

 

 

186

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SUMMARY

 

 

Assigned terminals

VDD(3.3V)

VDD(2.5V)

GND

Total terminals

186

9

20

25

240

12

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Image 12
Contents TNETX3270 ThunderSWITCH 24/3 ETHERNET Switch With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsWith 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports DescriptionThunderSWITCH 24/3 ETHERNET ContentsPGV Package TOP View ThunderSWITCH  24/3Terminal Internal Description Name RESISTOR³ 10-/100-Mbit/s MAC interface ports 24±26³ Terminal Internal Description Name ResistorTerminal Functions 10-/100-Mbit/s MAC interface ports 24±26 ²Sdram interface Dras DcasDclk DrasHost DIO interface Serial MII management PHY interface Eeprom interfaceJtag interface Power interface Summary of signal terminals by signal group functionMiscellaneous DIO register groups Internal Register and Statistics Memory MapVlan Detailed DIO Register Map Byte DIO AddressSIO VLAN1QID VLAN0QID VLAN3QID VLAN2QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN17QID VLAN16QID VLAN19QID VLAN18QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDIntenable TNETX3270 reset reinitializes the TNETX3270 0x40000x5FFFFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8State of DIO signals during hardware reset Interface descriptionReceiving/transmitting management frames Network management port Frame format on the NM port Vlan ID FCSTpid TCI CRCMII serial management interface PHY management Mbit/s and 10-/100-Mbit/s MAC interface receive controlGiant long frames Short framesReceive filtering of frames Data transmissionTransmit control Adaptive performance optimization APO transmit pacingReceive versus transmit priority Uplink pretaggingSource-Port Pretag Encoding Source PortReceived Pretag Port Assignments TAGPort 27 NM Eeprom interface Edio TNETX3270 Eclk SCL SDAGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag interface Jtag Instruction OpcodesHighz instruction LED interfaceHardware configurations LED Status Bit Definitions and Shift OrderLamp test Multi-LED displayMbit/s Interface Connections TNETX3270 TNETE2008 TerminalPort CLK Sync TXD3 M03TXD M04TXDM06TXD M03COLConnecting to TNETE2008 PHY² 10-/100-Mbit/s port configuration Switch TNETE2101 Terminal10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface ConnectionsSpeed Configuration ± MxxFORCE10 Duplex Configuration ± MxxFORCEHD10-/100-Mbit/s port configuration in a nonmanaged switch 10-/100-Mbit/s port configuration in a managed switch Sdram interface TNETX3270 Terminal Interface to SDRAMs Sdram Terminals Not Driven by the TNETX3270Terminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionTNETX3270 State Terminal During Reset SDRAM-type and quantity indicationInitialization RefreshFrame routing Vlan supportIale Address maintenance Ieee Std 802.1Q headers ± receptionIeee Std 802.1Q headers ± transmission Spanning-tree support Aging algorithmsFrame-routing determination Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April Port mirroring CDEPort trunking/load sharing Flow controlCollision-based flow control Ieee Std 802.3 flow controlPause frame reception Internal wrap test Duplex wrap test PHY TNETX3270Copy to uplink Recommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP MAX Unit Test measurement MIN MAX Unit Parameter MIN MAX Unit10-/100-Mbit/s MAC interface Timing requirements see Note 7 and Figure10-/100-Mbit/sreceive ports 24, 25 Timing requirements see Figure 10-/100-Mbit/stransmit ports 24, 25,Sdram command to command see Figure TdDA Delay time, from Dclk ↑ to DA Invalid Sdram subcycleDclk Dras DcasDIO/DMA interface DIO/DMA write cycleSDATA7± Z SDATA0 DIO/DMA read cycle Serial MII Management Read/Write Cycle Eeprom Parameter TNETX3150 TNETX3150A Unit MIN MAXTdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalid ² During hard reset, Ledclk runs continuouslyPower-up Oscin and Reset Timing requirements see Figure TsuRESET Setup time Low before Oscin ↑ThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice