Texas Instruments TNETX3270 Jtag interface, Jtag Instruction Opcodes, Highz instruction

Page 29

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS043B ± NOVEMBER 1997 ± REVISED APRIL 1999

JTAG interface

The TNETX3270 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones. All JTAG inputs and outputs are 3.3-V tolerant.

The following instructions are supported:

DEXTEST, BYPASS, and SAMPLE/PRELOAD

DHIGHZ and IDCODE

DPrivate (various private instructions are used by TI for test purposes)

The opcodes for the various instructions (6-bit instruction register) are shown in Table 8.

Table 8. JTAG Instruction Opcodes

INSTRUCTION	INSTRUCTION	JTAG
TYPE	NAME	OPCODE

Mandatory	EXTEST	000000

Mandatory	SAMPLE/PRELOAD	000001

Optional	IDCODE	000100

Optional	HIGHZ	000101

Optional	RACBIST	000110

Private	TI testing	Others

Mandatory	BYPASS	111111

HIGHZ instruction

When selected, the HIGHZ instruction causes all outputs and bidirectional pins to become high impedance. All pullup and pulldown resistors are disabled.

LED interface

This interface allows a visual status for each port to be displayed. In addition, the state of the internal flow control and fault functions are displayed along with 12 software-controllable LEDs.

Each port has a single LED, which can convey three states (see Table 9).

Table 9. LED States

STATE	DISPLAY

No link	Off

Link, but no activity	On

Activity (bits moving)	Flashing at 8 Hz

The interface is intended for use with external octal shift registers clocked with LEDCLK. Every 16th of a second, all the status bits are shifted out via LEDDATA.

The status bits are shifted out in one of two possible orders, as determined by slast in LEDControl, to ensure that systems that do not require all the LED status can be implemented with the minimum number of octal shift registers (see Table 10).

DIf slast = 0, the software-controlled status bits are shifted out before the port status bits.

DIf slast = 1, the software-controlled status bits are shifted out after the port status bits.

The fault status bit is shifted out last, enabling a minimal system that displays only the fault status to be implemented without any shift registers.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

29

Image 29

Contents With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S Ports TNETX3270 ThunderSWITCH 24/3 ETHERNET SwitchDescription With 24 10-MBIT/S Ports and 3 10-/100-MBIT/S PortsContents ThunderSWITCH 24/3 ETHERNETPGV Package TOP View  24/3 ThunderSWITCHTerminal Internal Description Name RESISTOR³ Terminal Internal Description Name Resistor 10-/100-Mbit/s MAC interface ports 24±26³10-/100-Mbit/s MAC interface ports 24±26 ² Terminal FunctionsDras Dcas Sdram interfaceDclk DrasHost DIO interface Jtag interface Serial MII management PHY interfaceEeprom interface Miscellaneous Power interfaceSummary of signal terminals by signal group function Vlan DIO register groupsInternal Register and Statistics Memory Map SIO Detailed DIO Register MapByte DIO Address VLAN3QID VLAN2QID VLAN1QID VLAN0QIDVLAN5QID VLAN4QID VLAN7QID VLAN6QIDVLAN19QID VLAN18QID VLAN17QID VLAN16QIDVLAN21QID VLAN20QID VLAN23QID VLAN22QIDTNETX3270 reset reinitializes the TNETX3270 0x40000x5FFF IntenableFindnode23±16 Findnode31±24 Findnode39±32 Findnode47±40 Findcontrol Findnode7±0 Findnode15±8Receiving/transmitting management frames State of DIO signals during hardware resetInterface description Network management port Frame format on the NM port FCS Vlan IDTpid TCI CRCMbit/s and 10-/100-Mbit/s MAC interface receive control MII serial management interface PHY managementGiant long frames Short framesData transmission Receive filtering of framesTransmit control Adaptive performance optimization APO transmit pacingUplink pretagging Receive versus transmit prioritySource Port Source-Port Pretag EncodingPort 27 NM Received Pretag Port AssignmentsTAG GND Eeprom interfaceEdio TNETX3270 Eclk SCL SDA Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Summary of Eeprom Load OutcomesJtag Instruction Opcodes Jtag interfaceHighz instruction LED interfaceLED Status Bit Definitions and Shift Order Hardware configurationsLamp test Multi-LED displayTNETX3270 TNETE2008 Terminal Mbit/s Interface ConnectionsM03TXD M04TXD Port CLK Sync TXD3M06TXD M03COLConnecting to TNETE2008 PHY² Switch TNETE2101 Terminal 10-/100-Mbit/s port configuration10-/100-Mbit/s MAC interfaces ports 24±26 100-Mbit/s Interface Connections10-/100-Mbit/s port configuration in a nonmanaged switch Speed Configuration ± MxxFORCE10Duplex Configuration ± MxxFORCEHD 10-/100-Mbit/s port configuration in a managed switch Sdram Terminals Not Driven by the TNETX3270 Sdram interface TNETX3270 Terminal Interface to SDRAMsTerminals Sdram Terminal Function TNETX3270 Held Sdram Terminal Terminal FunctionSDRAM-type and quantity indication TNETX3270 State Terminal During ResetInitialization RefreshIale Frame routingVlan support Ieee Std 802.1Q headers ± transmission Address maintenanceIeee Std 802.1Q headers ± reception Frame-routing determination Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS043B ± November 1997 ± Revised April CDE Port mirroringFlow control Port trunking/load sharingIeee Std 802.3 flow control Collision-based flow controlPause frame reception Internal wrap test PHY TNETX3270 Duplex wrap testCopy to uplink Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit Test measurement Parameter MIN MAX Unit MIN MAX Unit10-/100-Mbit/sreceive ports 24, 25 10-/100-Mbit/s MAC interfaceTiming requirements see Note 7 and Figure 10-/100-Mbit/stransmit ports 24, 25, Timing requirements see FigureSdram command to command see Figure Sdram subcycle TdDA Delay time, from Dclk ↑ to DA InvalidDclk Dras DcasSDATA7± Z SDATA0 DIO/DMA interfaceDIO/DMA write cycle DIO/DMA read cycle Serial MII Management Read/Write Cycle Parameter TNETX3150 TNETX3150A Unit MIN MAX Eeprom² During hard reset, Ledclk runs continuously TdLEDDATA Delay time, from LEDCLK↑ to 1st LED invalidTsuRESET Setup time Low before Oscin ↑ Power-up Oscin and Reset Timing requirements see FigureThRESET Hold time Low after Oscin ↑ TtOSCIN Transition time, Oscin rise and fallMechanical Data Important Notice